LAN91C100-FD-SS SMSC [SMSC Corporation], LAN91C100-FD-SS Datasheet - Page 32

• Manufacturer Part Number: LAN91C100-FD-SS
• Description: FEAST Fast Ethernet Controller with Full Duplex Capability
• Manufacturer: SMSC [SMSC Corporation]

This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. An enabled bit being
set will cause a hardware interrupt.
EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions. This bit
merges exception type of interrupt sources, whose service time is not critical to the execution speed of the low level drivers.
The exact nature of the interrupt can be obtained from the EPH Status Register (EPHSR), and enabling of these sources
can be done via the Control Register. The possible sources are:
RX_DISC INT - Set when the nRXDISC PIN COUNTER in the ERCV register increments to a value of FF. The RX_DISC
INT bit latches the condition for the purpose of being polled or generating an interrupt, and will only be cleared by writing the
acknowledge register with the RX_DISC INT bit set.
RX_OVRN INT - Set when 1) the receiver aborts due to an overrun due to a failed memory allocation, 2) the receiver
aborts due to a packet length of greater than 2K bytes, or 3) the receiver aborts due to the RCV DISCRD bit in the ERCV
register set. The RX_OVRN INT bit latches the condition for the purpose of being polled or generating an interrupt, and will
only be cleared by writing the acknowledge register with the RX_OVRN INT bit set.
ALLOC INT - Set when an MMU request for TX pages allocation is completed. This bit is the complement of the FAILED
bit in the ALLOCATION RESULT register. The ALLOC INT ENABLE bit should only be set following an allocation
command, and cleared upon servicing the interrupt.
TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the end of a sequence of
packets enqueued for transmission. This bit latches the empty condition, and the bit will stay set until it is specifically
cleared by writing the acknowledge register with the TX EMPTY INT bit set. If a real time reading of the FIFO empty is
desired, the bit should be first cleared and then read.
SMSC DS – LAN91C100FD REV. B
LINK - Link Test transition
CTR_ROL - Statistics counter roll over
TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific
reason will be reflected by the bits:
TXUNRN - Transmit underrun
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
RX_DISC
RX_DISC
OFFSET
OFFSET
INT
INT
0
C
D
ERCV INT
ERCV INT
0
INTERRUPT ACKNOWLEDGE
INTERRUPT MASK REGISTER
EPH INT
REGISTER
0
NAME
NAME
RX_OVRN
RX_OVRN
INT
INT
0
Page 32
ALLOC INT
0
READ/WRITE
WRITE ONLY
TYPE
TX EMPTY
TX EMPTY
TYPE
INT
INT
0
TX INT
TX INT
0
SYMBOL
SYMBOL
ACK
MSK
RCV INT
0
Rev. 01-20-06