LAN91C100-FD-SS SMSC [SMSC Corporation], LAN91C100-FD-SS Datasheet - Page 54

• Manufacturer Part Number: LAN91C100-FD-SS
• Description: FEAST Fast Ethernet Controller with Full Duplex Capability
• Manufacturer: SMSC [SMSC Corporation]

SMSC DS – LAN91C100FD REV. B
additional logic)
EISA BUS
nDAK<n>
nEXRDY
SIGNAL
nNOWS
(optional
nIOWC
nIORC
nEX32
BCLK
GND
VCC
THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES
LAN91C100FD
nDATACS
nRDYRTN
nCYCLE
nVLBUS
SIGNAL
nLDEV
LCLK
W/nR
Table 5 - EISA 32 Bit Slave Signal Connections
A1
nLDEV is a totem pole output. nLDEV is active on valid decodes
of LAN91C100FD pins A15-A4, and AEN=0. nNOWS is similar
to nLDEV except that it should go inactive on nSTART rising.
nNOWS can be used to request compressed cycles (1.5 BCLK
long, nRD/nWR will be 1/2 BCLK wide).
EISA Bus Clock. Data transfer clock for DMA bursts.
DMA Acknowledge. Active during Slave DMA cycles. Used by
the LAN91C100FD as nDATACS direct access to data path.
Indicates the direction and timing of the DMA cycles. High
during LAN91C100FD writes, low during LAN91C100FD reads.
Indicates slave DMA writes.
EISA bus signal indicating whether a slave DMA cycle will take
place on the next BCLK rising edge, or should be postponed.
nRDYRTN is used as an input in the slave DMA mode to bring
in EXRDY.
UNUSED PINS
Page 54
NOTES
Rev. 01-20-06