LAN91C100-FD-SS SMSC [SMSC Corporation], LAN91C100-FD-SS Datasheet - Page 48

• Manufacturer Part Number: LAN91C100-FD-SS
• Description: FEAST Fast Ethernet Controller with Full Duplex Capability
• Manufacturer: SMSC [SMSC Corporation]

The LAN91C100FD is envisioned to fit a few different bus types. This section describes the basic guidelines, system level
implications and sample configurations for the most relevant bus types.
architectures with a private SRAM bus.
FAST ETHERNET SLAVE ADAPTER
Slave non-intelligent board implementing 100 Mbps and 10 Mbps speeds.
Adapter requires:
a)
b)
c)
d)
e)
f)
Target systems:
a)
b)
c)
VL Local Bus 32 Bit SystemsVL Local Bus 32 bit systemsVL Local Bus 32 bit systems
On VL Local Bus and other 32 bit embedded systems the LAN91C100FD is accessed as a 32 bit peripheral in terms of the
bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions. Accesses to the
DATA REGISTER could use byte, word, or dword instructions.
SMSC DS – LAN91C100FD REV. B
LAN91C100FD chip
Four SRAMs (32k x 8 - 25ns)
Serial EEPROM (93C46)
Mbps ENDEC and transceiver chip
Mbps MII compliant PHY
Some bus specific glue logic
VL Local Bus 32 bit systems
High-end ISA or non-burst EISA machines
EISA 32 bit slave
nBE0 nBE1
nBE2 nBE3
nRDYRTN
nRESET
SIGNAL
VL BUS
A2-A15
nLRDY
M/nIO
nADS
W/nR
LCLK
nSRDY and some
nADS, nCYCLE
LAN91C100
nBE0 nBE1
nBE2 nBE3
nRDYRTN
SIGNAL
A2-A15
RESET
W/nR
LCLK
AEN
logic
Table 3 - VL Local Bus Signal Connections
APPLICATION CONSIDERATIONS
Address bus used for I/O space and register decoding, latched by
nADS rising edge, and transparent on nADS low time.
Qualifies valid I/O decoding - enabled access when low. This signal
is latched by nADS rising edge and transparent on nADS low time.
Direction of access. Sampled by the LAN91C100FD on first rising
clock that has nCYCLE active. High on writes, low on reads.
Ready return. Direct connection to VL bus.
nSRDY has the appropriate functionality and timing to create the VL
nLRDY except that nLRDY behaves like an open drain output most
of the time.
Local Bus Clock. Rising edges used for synchronous bus interface
transactions.
Connected via inverter to the LAN91C100FD.
Byte enables. Latched transparently by nADS rising edge.
Address Strobe is connected directly to the VL bus. nCYCLE is
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NOTES
All applications are based on buffered
Rev. 01-20-06