LAN91C100-FD-SS SMSC [SMSC Corporation], LAN91C100-FD-SS Datasheet - Page 37

• Manufacturer Part Number: LAN91C100-FD-SS
• Description: FEAST Fast Ethernet Controller with Full Duplex Capability
• Manufacturer: SMSC [SMSC Corporation]

SMSC DS – LAN91C100FD REV. B
1 ISSUE ALLOCATE MEMORY FOR TX - N
2 WAIT
3 LOAD TRANSMIT DATA - Copy the TX packet
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
5
6
7 SERVICE INTERRUPT - Read Interrupt Status
BYTES - the MMU attempts to allocate N bytes
of RAM.
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
Register. If it is a transmit interrupt, read the TX
Done Packet Number from the Fifo Ports
Register. Write the packet number into the
Packet Number Register.
status word is now readable from memory. If
status word shows successful transmission,
issue RELEASE packet number command to
free up the memory used by this packet.
Remove packet number from completion FIFO
by writing TX INT Acknowledge Register.
FOR
SUCCESSFUL
S/W DRIVER
TYPICAL FLOW OF EVENTS FOR TRANSMIT
The corresponding
COMPLETION
Page 37
The enqueued packet will be transferred to the
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duplex mode
only) state.
Upon transmit completion the first word in
memory is written with the status word. The
packet number is moved from the TX FIFO into
the TX completion FIFO. Interrupt is generated
by the TX completion FIFO being not empty.
MAC SIDE
Rev. 01-20-06