MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 212

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MC68HC908AS60ACFN

Manufacturer Part Number
MC68HC908AS60ACFN
Description
M68HC08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Serial Peripheral Interface (SPI)
delay will be no longer than a single SPI bit time. That is, the maximum delay between the write to SPDR
and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32
MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
212
SCK CYCLE
NUMBER
CPHA = 1
CPHA = 0
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
SCK
SCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
BUS
BUS
BUS
BUS
BUS
MOSI
TO SPDR
TO SPDR
TO SPDR
TO SPDR
WRITE
WRITE
WRITE
WRITE
Figure 19-6. Transmission Start Delay (Master)
TO SPDR
WRITE
EARLIEST LATEST
EARLIEST
EARLIEST
EARLIEST
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
SCK = INTERNAL CLOCK ÷ 128;
INITIATION DELAY
SCK = INTERNAL CLOCK ÷ 32;
128 POSSIBLE START POINTS
SCK = INTERNAL CLOCK ÷ 2;
SCK = INTERNAL CLOCK ÷ 8;
32 POSSIBLE START POINTS
2 POSSIBLE START POINTS
8 POSSIBLE START POINTS
MSB
1
BIT 6
2
LATEST
LATEST
LATEST
BIT 5
3
Freescale Semiconductor

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