MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 261

• Manufacturer Part Number: MC68HC908AS60ACFN
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

22.7.1 Port F Data Register
The port F data register contains a data latch for each of the seven port F pins.
PTF[6:0] — Port F Data Bits
TACH[5:2] — Timer A Channel I/O Bits
TBCH[1:0] — Timer B Channel I/O Bits
22.7.2 Data Direction Register F
Data direction register F determines whether each port F pin is an input or an output. Writing a logic 1 to
a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output buffer.
Freescale Semiconductor
These read/write bits are software programmable. Data direction of each port F pin is under the control
of the corresponding bit in data direction register F. Reset has no effect on PTF[6:0].
The PTF3–PTF0/TACH2 pins are the TIM input capture/output compare pins. The edge/level select
bits, ELSxB:ELSxA, determine whether the PTF3–PTF0/TACH2 pins are timer channel I/O pins or
general-purpose I/O pins. (See
The PTF5/TBCH1–PTF4/TBCH0 pins are the TIMB input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTF5/TBCH1–PTF4/TBCH0 pins are timer channel
I/O pins or general-purpose I/O pins. (See
Alternative
Function:
Address:
Address:
Data direction register F (DDRF) does not affect the data direction of port F
pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. (See
Reset:
Reset:
Read:
Read:
Write:
Write:
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Bit 7
Bit 7
R
R
R
R
0
0
0
Figure 22-18. Data Direction Register F (DDRF)
Figure 22-17. Port F Data Register (PTF)
= Reserved
= Reserved
DDRF6
PTF6
6
6
0
25.8.1 TIMA Status and Control
Table
TBCH1
DDRF5
PTF5
5
5
0
22-6).
20.8.1 TIMB Status and Control
NOTE
TBCH0
DDRF4
Unaffected by Reset
PTF4
4
4
0
TACH5
DDRF3
PTF3
3
3
0
Register).
TACH4
DDRF2
PTF2
2
2
0
DDRF1
TACH3
PTF1
Register).
1
1
0
DDRF0
TACH2
PTF0
Bit 0
Bit 0
0
Port F
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