MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 165
MC68HC912BD32CFU10
Manufacturer Part Number
MC68HC912BD32CFU10
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC68HC912BD32CFU10.pdf
(292 pages)
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SP0CR2 — SPI Control Register 2
19-sint
RESET:
1. The serial pin control 0 bit enables bidirectional configurations.
2. Slave output is enabled if DDS4 = 1, SS = 0 and MSTR = 0. (#1, #3)
3. Master output is enabled if DDS5 = 1 and MSTR = 1. (#2, #4)
4. SCK output is enabled if DDS6 = 1 and MSTR = 1. (#2, #4)
5. SS output is enabled if DDS7 = 1, SSOE = 1 and MSTR = 1. (#2, #4)
#1
#2
#3
#4
Pin Mode
Bidirectional
Bit 7
0
0
Normal
6
0
0
LSBF — SPI LSB First enable
SSWAI — SSI Stop in Wait Mode
SPC0 — Serial Pin Control 0
SPC0
Normally data is transferred most significant bit first.This bit does not
affect the position of the MSB and LSB in the data register. Reads and
writes of the data register will always have MSB in bit 7.
Read or write anytime.
This bit decides serial pin configurations with MSTR control bit.
Freescale Semiconductor, Inc.
0
1
For More Information On This Product,
0 = Data is transferred most significant bit first
1 = Data is transferred least significant bit first
0 = SSI clock operate normally
1 = Halt SSI clock generation when in Wait mode
(1)
5
0
0
Go to: www.freescale.com
MSTR
0
1
0
1
Serial Interface
4
0
0
Table 32
Slave Out
Master In
Slave I/O
MISO
GPI/O
3
0
0
(2)
Master Out
Master I/O
MOSI
Slave In
GPI/O
2
0
0
(3)
SSWAI
Serial Peripheral Interface (SPI)
SCK Out
SCK Out
SCK In
SCK In
SCK
1
0
MC68HC912BD32 Rev 1.0
(4)
SPC0
Bit 0
0
SS I/O
SS I/O
SS In
SS In
Serial Interface
SS
(5)
$00D1
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