MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 59

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MC68HC912BD32CFU10

Manufacturer Part Number
MC68HC912BD32CFU10
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1-bus
Contents
Introduction
Detecting Access Type from External Signals
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . 55
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Internally the MC68HC912BD32 has full 16-bit data paths, but
depending upon the operating mode and control registers, the external
bus may be 8 or 16 bits. There are cases where 8-bit and 16-bit
accesses can appear on adjacent cycles using the LSTRB signal to
indicate 8- or 16-bit data.
The external signals LSTRB, R/W, and A0 can be used to determine the
type of bus access that is taking place. Accesses to the internal RAM
module are the only type of access that produce LSTRB=A0=1, because
the internal RAM is specifically designed to allow misaligned 16-bit
accesses in a single cycle. In these cases the data for the address that
was accessed is on the low half of the data bus and the data for address
+ 1 is on the high half of the data bus (data order is swapped).
Freescale Semiconductor, Inc.
For More Information On This Product,
Bus Control and Input/Output
Go to: www.freescale.com
Bus Control and Input/Output
Bus Control and Input/Output
MC68HC912BD32 Rev 1.0

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