MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 74

• Manufacturer Part Number: MC68HC912BD32CFU10
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Flash EEPROM
MC68HC912BD32 Rev 1.0
ERAS — Erase Control
LAT — Latch Control
ENPE — Enable Programming/Erase
This bit can be read anytime or written when ENPE = 0. When set, all
locations in the array will be erased at the same time. The boot block
will be erased only if BOOTP = 0. This bit also affects the result of
attempted array reads. See
ERAS cannot change if ENPE is set.
This bit can be read anytime or written when ENPE = 0. When set, the
Flash EEPROM is configured for programming or erasure and, upon
the next valid write to the array, the address and data will be latched
for the programming sequence. See
array reads. A high voltage detect circuit on the V
assertion of the LAT bit when the programming voltage is at normal
levels.
ENPE can be asserted only after LAT has been asserted and a write
to the data and address latches has occurred. If an attempt is made
to assert ENPE when LAT is negated, or if the latches have not been
written to after LAT was asserted, ENPE will remain negated after the
write cycle is complete.
The LAT, ERAS and BOOTP bits cannot be changed when ENPE is
asserted. A write to FEECTL may only affect the state of ENPE.
Attempts to read a Flash EEPROM array location in the Flash
EEPROM module while ENPE is asserted will not return the data
addressed. See
Flash EEPROM module control registers may be read or written while
ENPE is asserted. If ENPE is asserted and LAT is negated on the
same write access, no programming or erasure will be performed.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Flash EEPROM configured for programming
1 = Flash EEPROM configured for erasure
0 = Programming latches disabled
1 = Programming latches enabled
0 = Disables program/erase voltage to Flash EEPROM
1 = Applies program/erase voltage to Flash EEPROM
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Flash EEPROM
Table 1
for more information.
Table 1
for more information. Status of
Table 1
for the effects of LAT on
FP
pin will prevent
6-flash