MC68HC912BD32CFU10 FREESCALE [Freescale Semiconductor, Inc], MC68HC912BD32CFU10 Datasheet - Page 204

• Manufacturer Part Number: MC68HC912BD32CFU10
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Module
Configuration
Register (MCR)
Byteflight™ Module
MC68HC912BD32 Rev 1.0
HARDRESET
$xx00
MCR
W
R
NOTE:
SFTRES
BIT 7
1
Figure 36 General Configuration Register (MCR)
Setting SFTRES and writing to other bits in the MCR can be done in
separate instructions only! Trying to set SFTRES and change other bits
together will change the SFTRES only, the other bits will be unchanged.
Clearing SFTRES and writing to other bits in the MCR can be done in
one instruction.
SFTRES — Soft Reset
MASTER — Master Select
ALARM — Master Alarm Pulses
MASTER*
BIT 6
When this bit is set by the CPU, the module immediately enters the
soft reset state. Any ongoing transmission or reception is aborted and
synchronization to the bus is lost.
When this bit is cleared by the CPU, the interface will start to connect
back to the bus. It will be synchronized after the next SYNC pulse on
the bus.
This bit selects the node as bus master or as bus slave. Writing to this
bit is allowed during soft reset only.
If the Master bit and the Alarm bit are set, ALARM pulses are
transmitted.
The ALARM bit is reset after 255ms - 256ms if it has not been set
again by the CPU within that period. The Alarm bit can be set and
cleared any time.
Freescale Semiconductor, Inc.
0
For More Information On This Product,
1 = Soft reset state.
0 = Normal operation.
1 = The interface is a master and generates the SYNC pulses.
0 = The interface is a slave and verifies the SYNC pulses.
1 = The interface generates ALARM pulses.
0 = The interface generates normal SYNC pulses.
ALARM
BIT 5
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0
Byteflight™ Module
SLPAK
BIT 4
0
SLPRQ
BIT 3
0
WPULSE*
BIT 2
0
SSWAI
BIT 1
0
BIT 0
0
0
34-sibus