ISL6341 INTERSIL [Intersil Corporation], ISL6341 Datasheet - Page 11

• Manufacturer Part Number: ISL6341
• Description: 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
• Manufacturer: INTERSIL [Intersil Corporation]

PGOOD
The PGOOD function output monitors the output voltage
using the same VOS pin and resistor divider of the
undervoltage and overvoltage protection, but with separate
comparators for each. The rising OV trip point (10% above
0.8V = 0.88V nominal on VOS) and the falling UV trip point
(10% below 0.8V = 0.72V nominal on VOS) will trip sooner
than the protection, in order to give an early warning to a
possible problem. The response time of the comparators
should be less than 1µs; the separate VOS input is not slowed
down by the compensation on the FB pin. It is NOT
recommended to connect the VOS pin to the FB pin, in order
to share the resistor divider. If the VOS pin is accidentally
disconnected, a small bias current on-chip will force an
overvoltage condition.
Figure 9 shows how the PGOOD output responds to a ramp
that trips in each direction (without reaching either protection
trip point at ±25%); PGOOD is valid (high) as long as V
(and thus VOS) is within the ±10% window.
The PGOOD output is an open-drain pull-down NMOS
device; it can deliver 4.0mA of sink current at 0.3V when
power is NOT GOOD. A pull-up resistor to an external supply
voltage sets the high level voltage when power is GOOD. The
supply should be ≤6.0V, and is usually the one that powers
the logic monitoring the PGOOD output. If PGOOD function is
not used, the PGOOD pin can be left floating.
The PGOOD pin will be held low once V
POR trip point, and during soft-start (but if the PGOOD supply
is up before or with V
logic has enough voltage to turn on the output). Once the
soft-start ramp is done (V
100% of their final value), the PGOOD pin will be allowed to
go high, if the output voltage is within the expected window.
There is no additional delay after soft-start is done.
Note that the overcurrent protection does directly affect the
PGOOD output, before the output voltage monitoring would
sense when V
undervoltage protection circuits don’t directly effect PGOOD,
110%
GND>
GND>
90%
FIGURE 9. PGOOD UNDERVOLTAGE AND OVERVOLTAGE
V
PGOOD (2V/DIV)
OUT
OUT
(0.25V/DIV)
drops 10%. The overvoltage and
CC
, it may be pulled high initially until the
OUT
, VOS and FB should each be at
11
ISL6341, ISL6341A, ISL6341B, ISL6341C
CC
is above the rising
OUT
but since the PGOOD UV and OV windows are tighter, the
PGOOD output should already be low by the time either
protection is tripped.
Switching Frequency
The switching frequency is a fixed 300kHz for the ISL6341,
ISL6341C and 600kHz for the ISL6341A, ISL6341B. It
cannot be adjusted externally, and the various soft-start
delays and ramps are fixed at the same times for either
frequency.
Output Voltage Selection
The output voltage can be programmed to any level between
the 0.8V internal reference, up to the V
85% duty cycle restriction for the ISL6341, ISL6341C (75%
for the ISL6341A, ISL6341B). Additional duty cycle margin
due to the r
load needs to be factored in as well.
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage, and feed it
back to the inverting input of the error amp. See the “Typical
Application” schematic on page 3 for more detail; R
upper resistor; R
lower one. The recommended value for R
(±1% for accuracy) and then R
to Equation 2. Since R
(see “Feedback Compensation” on page 13), it is often
easier to change R
that way the compensation calculations do not need to be
OCP
ISL6341
ISL6341B
OCP
ISL6341A
ISL6341C
UVP
(-25%)
OVP
(+25%)
PGOOD
(UV; -10%)
PGOOD
(OV; +10%)
PGOOD
(OCP)
PROTECTION
DS(ON)
TABLE 2. PROTECTION SUMMARY
V OUT latches off;
LGATE and UGATE low.
Infinite retries; wait ~10ms,
and try a new Soft-Start ramp.
ISL6341C has UVP disabled
V OUT latches off;
LGATE and UGATE low.
ISL6341C has UVP disabled
V OUT latches off;
UGATE low;
LGATE goes low and high to
keep V OUT within 50% and
125% of nominal.
VOS pin open will trigger OV.
PGOOD goes low if VOS is
10% too low.
PGOOD goes low if VOS is
10% too high.
PGOOD goes low if OCP trips after SS
OFFSET
OFFSET
drop across the upper FET at maximum
ACTION TAKEN
S
is part of the compensation circuit
(shortened to R
to change the output voltage;
OFFSET
IN
is chosen according
O
supply, with the
S
POR or
COMP/EN
POR or
COMP/EN
after SS
ramp
POR
after SS
ramp
after SS
ramp
ramp
ENABLED
below) is the
is 1kΩ to 5kΩ
AFTER
December 2, 2008
S
is the
FN6538.2
POR or
COMP/EN
Not
Applicable
POR
POR
POR or
COMP/EN
POR or
COMP/EN
POR or
COMP/EN
or good
SS ramp
RESET
BY