ISL6341 INTERSIL [Intersil Corporation], ISL6341 Datasheet - Page 9

• Manufacturer Part Number: ISL6341
• Description: 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
• Manufacturer: INTERSIL [Intersil Corporation]

.
Figure 6 shows the ISL6341A, ISL6341C output response
during a retry of an output shorted to GND. At time t0, the
output has been turned off, due to sensing an overcurrent
condition. There are two internal soft-start delay cycles (t1
and t2) to allow the MOSFETs to cool down, to keep the
average power dissipation in retry at an acceptable level. At
time t2, the output starts a normal soft-start cycle, and the
output tries to ramp. If the short is still applied, and the
current reaches the OCSET trip point any time during
soft-start ramp period, the output will shut off and return to
time t0 for another delay cycle. The retry period is thus two
dummy soft-start cycles plus one variable one, which
depends on how long it takes to trip the sensor each time.
Figure 6 shows an example where the output gets about
half-way up before shutting down; therefore, the retry (or
hiccup) time will be around 12ms. The minimum should be
nominally 9.6ms and the maximum 14.4ms. If the short
condition is finally removed, the output should ramp up
normally on the next t2 cycle.
Starting up into a shorted load looks the same as a retry into
that same shorted load. In both cases, OCP is always
enabled during soft-start; once it trips, it will go into retry
(hiccup) mode. The retry cycle will always have two dummy
time-outs, plus whatever fraction of the real soft-start time
passes before the detection and shut-off; at that point, the
logic immediately starts a new two dummy cycle time-out.
Both OCP and UVP protect against shorts to GND, but the
responses (and recovery from) are different, as shown in
Table 2. For some combinations of output components and
shorting method, it may be difficult to predict which
protection will trip first (output voltage going too low, or
current going too high). The ISL6341C removes that
uncertainty by disabling the UVP, and relying only on the
OCP. Note that for the other 3 versions, if OCP trips first, it
locks out the UVP from also tripping, so that only the OCP
response (and recovery) are active.
GND>
GND>
0A>
OC
FIGURE 5. OCP TIMING (ISL6341A, ISL6341C)
I
INDUCTOR
LGATE (12V/DIV)
UGATE (24V/DIV)
(10A/DIV)
9
ISL6341, ISL6341A, ISL6341B, ISL6341C
OVERCURRENT EQUATIONS
For all the ISL6341x, versions, the overcurrent function will
trip at a peak inductor current (I
Equation 1:
where I
typical). The OC trip point varies in a system mainly due to
the MOSFET’s r
temperature). To avoid overcurrent tripping in the normal
operating load range, find the R
Equation 1 with:
For an equation for the ripple current see “Output Inductor
Selection” on page 15.
The range of allowable voltages detected (I
is 0mV to 550mV; but the practical range for typical
MOSFETs is smaller. If the voltage drop across R
set too low (< ~20mV), that can cause almost continuous
OCP tripping. It would also be very sensitive to system noise
and in-rush current spikes, so it should be avoided. The
maximum setting is 550mV, but most of the recommended
MOSFETs for the ISL6341x are not expected to handle the
power of the maximum trip point.
There is no way to disable the OCP, but setting it above the
maximum value (>600mV) will come close; for most cases, it
should be high enough (compared to the normal expected
range) to appear disabled. No resistor at all could give the
clamped maximum value (unless the loading on the LGATE
prevents charging the node fully). But there is no low-voltage
clamp on LGATE, so it could rise to over 3V and turn-on for
I
PEAK
1. The maximum r
2. The minimum I
3. Determine I
GND>
FIGURE 6. OCP RETRY OPERATION (ISL6341A, ISL6341C)
temperature.
Table” on page 5.
where ΔI is the output inductor ripple current.
=
OCSET
t0
I
-------------------------------------------------
OCSET
INTERNAL SOFT-START RAMP DELAYS
4.8ms
r
DS ON
is the internal OCSET current source (10µA
PEAK
DS(ON)
xR
(
OCSET
OCSET
DS(ON)
)
for
t1
variations (over process, current and
I
PEAK
from the “Electrical Specification
4.8ms
at the highest junction
PEAK)
OCSET
>
I
OUT MAX
0ms TO 4.8ms
t2
determined by
(
resistor from
(0.5V/DIV)
OCSET
V
)
OUT
+
t0
(
--------- -
ΔI
2
December 2, 2008
4.8ms
)
OCSET
*R
,
OCSET
FN6538.2
(EQ. 1)
is
)