ISL6341 INTERSIL [Intersil Corporation], ISL6341 Datasheet - Page 5

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ISL6341

Manufacturer Part Number
ISL6341
Description
5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet

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Electrical Specifications
NOTES:
Functional Pin Description
VCC (Pin 6)
This pin provides the bias supply for the ISL6341x, as well
as the lower MOSFET’s gate. An internal regulator will
supply bias as VCC rises above 5V, but the LGATE/OCSET
will still be sourced by VCC. Connect a well-decoupled 5V to
12V supply to this pin.
FB (Pin 8)
This pin is the inverting input of the internal error amplifier. Use
FB, in combination with the COMP/EN pin, to compensate the
voltage-control feedback loop of the converter. A resistor divider
from V
VOS (Pin 9)
This input pin monitors the regulator output for OV and UV
protection, and PGOOD (OV and UV). Connect a resistor
divider from V
the FB resistor divider. It is not recommended to share one
divider for both FB and VOS; the response to a fault may not
be as quick or robust. There is a small pull-up bias current
on the pin; if the VOS pin is not connected, the OV protection
would be tripped to protect the load.
GND (Pin 5)
This pin represents the signal and power ground for the IC.
This pin is the high current connection, and should be tied to
the ground island/plane through the lowest impedance
Upper Gate Sink Impedance
Lower Gate Source Impedance
Lower Gate Sink Impedance
PROTECTION/DISABLE
OCSET Current Source
Enable Threshold (COMP/EN pin)
VOS Rising Trip (PGOOD OV; +10%)
VOS Rising Trip (PGOOD OV) Hysteresis
VOS Falling Trip (PGOOD UV; -10%)
VOS Falling Trip (PGOOD UV) Hysteresis
VOS Rising Threshold (OV; +25%)
VOS Falling Threshold (UV; -25%)
(Note 5)
VOS Threshold (OV; 50% of V
VOS Bias Current
PGOOD
3. Limits should be considered typical and are not production tested.
4. Limits established by characterization and are not production tested.
5. The UVP is disabled on the ISL6341C; no trip point is measured.
OUT
to FB to GND is used to set the regulation voltage.
PARAMETER
OUT
to VOS to GND, with the same ratio as
OUT
5
Test Conditions: V
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
)
ISL6341, ISL6341A, ISL6341B, ISL6341C
R
R
SYMBOL
R
V
I
UG-SNKl
LG-SRCl
LG-SNKl
OCSET
ENABLE
CC
V
V
V
LGATE/OCSET = 0V
VOS = 0.25V
I
PGOOD
= 12V, T
CC
CC
CC
= 5V; I = 50mA
= 5V; I = 50mA
= 5V; I = 50mA
= 4mA
J
= 0°C to +85°C, Unless Otherwise Noted. Parameters with MIN and/or MAX
TEST CONDITIONS
connection available. The metal pad under the package
should also be connected to the GND plane for thermal
conductivity, but does not conduct any current.
PHASE (Pin 2)
Connect this pin to the source of the upper MOSFET, and
the drain of the lower MOSFET. It is used as the sink for the
UGATE driver, and to monitor the voltage drop across the
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry
to determine when the upper MOSFET has turned off.
UGATE (Pin 3)
Connect this pin to the gate of upper MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT (Pin 1)
This pin provides ground referenced bias voltage to the upper
MOSFET driver. A bootstrap circuit is used to create a voltage
suitable to drive an N-Channel MOSFET (equal to V
the BOOT diode voltage drop), with respect to PHASE.
COMP/EN (Pin 7)
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/EN, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.
0.683
0.868
0.980
0.580
0.380
-1500
0.708
0.10
MIN
9
0.700
0.880
0.720
1.000
0.600
0.400
-250
TYP
0.18
1.7
1.5
1.1
10
16
16
0.717
0.888
0.732
1.020
0.620
0.410
MAX
-100
0.30
11
December 2, 2008
GD
UNITS
FN6538.2
mV
mV
µA
nA
minus
Ω
Ω
Ω
V
V
V
V
V
V
V

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