ISL6341 INTERSIL [Intersil Corporation], ISL6341 Datasheet - Page 14

• Manufacturer Part Number: ISL6341
• Description: 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
• Manufacturer: INTERSIL [Intersil Corporation]

The compensation network consists of the error amplifier
(internal to the ISL6341x) and the external R
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R
C
poles and zeros of the compensation network:
It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. Equations 8 and 9 describe the
frequency response of the modulator (G
compensation (G
4. Select a value for R
5. Calculate C
6. Calculate C
7. Calculate R
3
) in Figure 13. Use the following guidelines for locating the
R
C
value for R
setting the output voltage via an offset resistor connected
to the FB pin (R
be followed as presented in Equation 4.
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
such that F
times f
Change the numerical factor to reflect desired placement
of this pole. Placement of F
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
R
C
3
1
2
2
=
=
=
=
------------------- -
---------------------------------------------- -
2π R
f
---------- - 1
F
-------------------------------------------- -
d
SW
------------------------------------------------------- -
2π R
SW
LC
V
MAX
R
0
OSC
⋅
⋅
1
; typically 0.1 to 0.3 of f
–
). f
P2
2
1
2
2
3
⋅
2
V
such that F
⋅
SW
for desired converter bandwidth (F
⋅
such that F
such that F
1
⋅
FB
0.5 F
is placed below f
R
IN
C
C
o
1
1
) and closed-loop response (G
1
⋅
represents the switching frequency.
⋅
LC
⋅
in Figure 13), the design procedure can
⋅
F
F
F
LC
1
0
LC
CE
(to adjust, change the 0.5 factor to
(1kΩ to 5kΩ, typically). Calculate the
–
Z1
P1
Z2
1
14
C
is placed at a fraction of the F
is placed at F
is placed at F
3
P2
=
SW
0dB
lower in frequency helps
---------------------------------------------- -
2π R
CE
SW
1
ISL6341, ISL6341A, ISL6341B, ISL6341C
, R
(typically, 0.5 to 1.0
⋅
/F
and 180°. The
) and adequate phase
2
LC
MOD
3
, R
⋅
1
, the lower the F
1
0.7 f
LC
LC
CE
3
to R
), feedback
, C
).
. Calculate C
⋅
.
1
SW
3
, C
, C
CL
0
2
1
). If
, and
):
(EQ. 5)
to C
(EQ. 4)
(EQ. 6)
(EQ. 7)
LC
Z1
3
3
,
G
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 14 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previous guidelines should yield
a compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log graph of Figure 14 by adding the modulator gain, G
dB), to the feedback compensation gain, G
equivalent to multiplying the modulator transfer function and the
compensation transfer function and then plotting the resulting
gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
G
G
F
F
FIGURE 14. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
MOD
CL
Z1
Z2
FB
0
f ( )
f ( )
=
=
LOG
f ( )
20
----------------------------- -
2π
----------------------------------------------- -
2π
=
=
log
=
⋅
G
-------------------------------------------------- - ⋅
s f ( )
⋅
⋅
----------------------------------------------------------------------------------------------------------------------- -
(
1
R
(
MOD
d
----------------------------- -
1
1
⎛
⎜
⎜
⎝
R
2
MAX
R
------- -
R
+
+
1
V
⋅
2
1
⋅
s f ( )
s f ( )
R
1
+
C
⎞
⎟
⎟
⎠
OSC
f ( ) G
1
1
R
⋅
⋅
3
V
⋅
⋅
⋅
(
F
)
R
R
C
IN
Z1
1
⋅
3
2
1
FB
C
F
+
F
⋅
⋅
LC
P2
⋅
+
3
Z2
----------------------------------------------------------------------------------------
1
C
s f ( )
C
f ( )
F
C
3
+
1
P1
2
against the capabilities of the error
)
s f ( )
)
⋅
⋅
⎛
⎜
⎝
F
F
(
=
1
CE
R
P1
F
⋅
1
+
------------------------------------------- -
2π
P2
(
1
CL
E
+
s f ( )
F
where s f ( )
+
⋅
R
+
=
0
R
, is constructed on the log-
3
s f ( ) E C
F
D
2
20
⋅
----------------------------- -
2π
)
P2
R
) C
⋅
⋅
1
log
2
⋅
C
------------------- -
C
C
G
⋅
⋅
,
3
1
⋅
1
R
CL
COMPENSATION GAIN
1
d
---------------------------------
⎛
⎜
⎝
OPEN LOOP E/A GAIN
FB
+
+
3
⋅
⋅
------------------- -
C
CLOSED LOOP GAIN
MAX V
G
C
C
⋅
s
C
V
1
MODULATOR GAIN
MOD
1
2
C
2
(in dB). This is
2
OSC
=
+
⋅
f ( ) L C
3
FREQUENCY
C
C
⋅
2π f j
2
December 2, 2008
2
⋅
⎞
⎟
⎠
IN
⋅ ⋅
⎞
⎟
⎠
⋅
G
MOD
FB
(EQ. 9)
FN6538.2
(EQ. 8)
(in