ISL6341 INTERSIL [Intersil Corporation], ISL6341 Datasheet - Page 12

• Manufacturer Part Number: ISL6341
• Description: 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
• Manufacturer: INTERSIL [Intersil Corporation]

repeated. If V
Output voltages less than 0.8V are not available.
The VOS pin is expected to see the same ratio for its resistor
divider; R
(±1% for accuracy) range. To simplify the BOM, R
should match R
If margining (or similar programmability) is added externally
(using a switch to change the effective lower resistor value),
the same method may be needed on the VOS pin resistor
divider. If the new VOUT (FB) is shifted too much compared
to the VOS trip, then PGOOD or UV/OV will be more likely to
trip in one direction (and less likely in the other).
Input Voltage Considerations
The “Typical Application” diagram on page 3 shows a
standard configuration where V
includes the standard 5V (±10%) or 12V (±20%) power
supply ranges. The gate drivers use the V
LGATE, and V
is an internal 5V regulator for bias.
The V
as V
sources, such as outputs of other regulators. If V
up first, and the V
initialization is done, then undervoltage will trip at the end of
soft-start (and will not recover without toggling V
COMP/EN will not restart it). Therefore, either the supplies
must be turned on in the proper order (together, or V
or the COMP/EN pin should be used to disable V
supplies are ready.
Figure 10 shows a simple sequencer for this situation. If V
powers up first, Q
Q
on, the resistor divider R
on, which will turn off Q
V
R
OUT
O
2
on, keeping the ISL6341x in shut-down. When V
=
CC
=
IN
----------------------------------
V
, but can also run off a separate supply or other
R
OUT
0.8V
to the upper MOSFET can share the same supply
S
VOS1
•
0.8V
–
•
FIGURE 10. SEQUENCER CIRCUIT
OUT
0.8V
(
---------------------------
GD
R
should also be chosen in the 1kΩ to 5kΩ
S
S
R
R
, and R
R
IN
1
(also 5V to 12V) for BOOT/UGATE. There
1
+
2
= 0.8V, then R
O
V
will be off and R
R
IN
or V
O
)
2
1
VOS2
GD
, and release the shut-down.
R
Q
and R
3
1
V
CC
are not present by the time the
12
should match R
CC
2
TO COMP/EN
OFFSET
Q
determines when Q
2
is 5V to 12V, which
3
ISL6341, ISL6341A, ISL6341B, ISL6341C
pulling to V
can be left open.
CC
voltage for
OFFSET
CC
OUT
CC
CC
VOS1
; toggling
CC
IN
will turn
powers
until all
1
(EQ. 2)
.
turns
turns
last),
CC
If V
ISL6341x will start-up as soon as V
V
NFET’s or NPN’s or even some logic IC’s can be used as Q
or Q
low leakage when off (open-drain or open-collector) so as
not to interfere with the COMP output. The V
should be reviewed over process and temperature variations
to insure that it will work properly under all conditions. Q
should be placed near the COMP/EN pin.
The V
the 0.8V reference). It can be as high as 20V (for V
below V
some restrictions for running high V
The first consideration for high V
voltage of 36V. The V
voltage - minus the diode drop), plus any ringing (or other
transients) on the BOOT pin must be less than 36V. If V
20V, that limits V
The second consideration is the maximum voltage ratings
for V
V
14.4V, then both V
separately. They can be derived from V
regulator or equivalent), or they can be independent. In
either case, they must satisfy the power supply sequencing
requirements noted earlier (either power-up in the proper
order, or use a sequencer to disable the output until they are
all ready).
The third consideration for high V
duty cycles (such as 20V in to 1.0V out, for 5% duty cycle)
require component selection compatible with that choice
(such as low r
filter, and compensation values to match). At the other
extreme (for example, 20V in to 12V out), the upper
MOSFET needs to be lower r
maximum duty cycle restriction. In all cases, the input and
output capacitors and both MOSFETs must be rated for the
voltages present.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
ENABLE
IN
IN
is above the maximum operating range for V
2
CC
. But Q
powers up first, Q
IN
IN
and BOOT-PHASE (for V
range can be as low as ~1.5V (for V
trip point is 0.7V nominal, so a wide variety of
, limited by the maximum duty cycle). There are
2
DS(ON)
should pull down hard when on, and must be
GD
CC
plus ringing to 16V.
IN
lower MOSFET, a good LC output
and V
(as seen on PHASE) plus V
1
will be on, turning Q
GD
DS(ON)
need to be supplied
IN
IN
GD
is the maximum BOOT
CC
IN
is duty cycle. Very low
); both are set at 15V. If
. There is also the
voltage.
comes up. The
IN
(using a linear
th
OUT
2
(or V
off; so the
December 2, 2008
CC
as low as
be
OUT
GD
of
) of Q
FN6538.2
(boot
IN
2
just
is
1
2