DS567 XILINX [Xilinx, Inc], DS567 Datasheet - Page 13

• Manufacturer Part Number: DS567
• Description: DDR2 Memory Controller for PowerPC 440 Processors
• Manufacturer: XILINX [Xilinx, Inc]

DS567 (v1.1.1) March 31, 2008
Read Datapath
As outlined in XAPP858: High-Performance DDR2 SDRAM Interface in Virtex-5 Devices, the read
datapath comprises several flip-flop stages (ranks) over which read data from the DDR2 memory is
transferred from the DQS strobe domain to the internal FPGA (CLK0) clock domain. It also includes the
local I/O clock network for distributing the DQS for the initial data capture, and circuitry to ensure robust
data capture on the last transfer of a read burst:
•
•
•
•
The read datapath is shown in
X-Ref Target - Figure 5
DQS
DQ
Rank 1 Capture: Initial capture of DQ with DQS using the IOB IDDR flip-flop and IDELAY
elements. The differential DQS pair must be placed on a clock-capable I/O pair and is distributed
through the local BUFIO network to each of the corresponding DQ IDDR capture flip-flops. The
IDDR generates two single-data-rate signals at its Q1 and Q2 outputs. Both Q1 and Q2 outputs
are clocked by the falling edge of DQS because:
♦
♦
Rank 2 Capture: The IDDR captures the data from the DDR2 memory, which is in the double-data-
rate domain, and generates two single-data-rate streams at its Q1 and Q2 outputs.The outputs of
the IDDR are transferred to flip-flops that are clocked by the rising or falling edge of CLK0. These
flip-flops are located in the CLBs. There are two possible sets of flip-flops that each IDDR output
can be transferred to. This allows synchronization of the IDDR outputs to either edge of CLK0 and
reduces the maximum number of IDELAY taps required to perform timing alignment.
Rank 3 Capture: The output of Rank 2 flip-flops clocked by the falling edge of CLK0 are transferred
to flip-flops clocked by the rising edge of CLK0. In addition, the multiplexer for each DQ capture
circuit is set to choose the appropriate synchronization path used.
DQS Gate Circuit: This circuit disables the clock enable for each DQ IDDR at the end of a read
burst to prevent any glitches associated with the DQS strobe being 3-stated by the memory from
clocking the IDDR flip-flop. There is one such circuit per DQS group.
The IDDR is configured in SAME_EDGE mode
The DQS is inverted before clocking the IDDR
IDELAY
IDELAY
BUFIO
DQS Gate
Circuit
IDDR
D Q1
CE
Q2
Figure
IOB
CLB
5.
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Figure 5: Read Datapath
DDR2 Memory Controller for PowerPC 440 Processors
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
D
D
Q
Q
Read Pipeline
Registers
Optional
D
D
D
Q
Q
Q
Read Data
Rise/Fall
DS567_05_010708
CLK 0
FIFOs
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