DS567 XILINX [Xilinx, Inc], DS567 Datasheet - Page 2

• Manufacturer Part Number: DS567
• Description: DDR2 Memory Controller for PowerPC 440 Processors
• Manufacturer: XILINX [Xilinx, Inc]

DDR2 Memory Controller for PowerPC 440 Processors
2
Functional Description
The PPC440MC DDR2 Memory Controller interfaces directly to the PowerPC processor through the
MCI (see
controller interface, users should use the relevant optimal UCF provided in the EDK PCORE directory.
There is only one optimal UCF for each device/package/processor combination.
X-Ref Target - Figure 1
I/O Signals
Table 1
Table 1: PPC440MC DDR2 Memory Controller I/O Signal Description
MIMCREADNOTWRITE
MIMCADDRESS[0:35]
MIMCADDRESSVALID
MIMCWRITEDATA[0:127]
MIMCBYTEENABLE[0:15]
MIMCWRITEDATAVALID
MIMCBANKCONFLICT
Interface
Interface
Control
FCM
defines the PPC440MC DDR2 Memory Controller signals.
Figure 1: PPC440 MCI and PPC440MC DDR2 Memory Controller Block Diagram
Figure
Virtex-5 Embedded Processor Block
Signal Name
Control
Control
CPM/
APU
1). To achieve hardware functionality and maximum performance with the memory
PowerPC 440
Processor
Interface
DCR
DCR
DCUWR
DCURD
ICURD
Interface
MCI
MCI
MCI
MCI
MCI
MCI
MCI
PPC440 MCI Signals
www.xilinx.com
Signal
Type
I
I
I
I
I
I
I
MCI
Status
Initial
DMA
DMA
DMA
DMA
This signal indicates if the operation is a
read or a write
Address bus
When asserted, this signal indicates the
data on the address bus is valid
Data bus
Byte enable for the data on the data bus
When asserted, this signal indicates the
data on the data bus is valid
This signal is asserted if the bank being
accessed is different from the bank
accessed in the previous command
DS567 (v1.1.1) March 31, 2008
LocalLink0
LocalLink1
SPLB0
Memory
Controller
Interface
MPLB
SPLB1
LocalLink2
LocalLink3
Description
DDR Memory
PPC440MC
Controller
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