DS567 XILINX [Xilinx, Inc], DS567 Datasheet - Page 21

• Manufacturer Part Number: DS567
• Description: DDR2 Memory Controller for PowerPC 440 Processors
• Manufacturer: XILINX [Xilinx, Inc]

DS567 (v1.1.1) March 31, 2008
In
presents a command for bank 0 in clock 2 and asserts the conflict bit. Bank 0 has already been opened
by the PPC440MC DDR2 Memory Controller. The conflict is a fake conflict. The PPC440MC DDR2
Memory Controller does not deassert the MCMIADDRREADYTOACCEPT signal. Internal_bank0 now
holds bank 0, indicating it is the most recently used bank. The commands presented in clocks 8, 15, and
22 are also fake conflicts. In clock 29, the MCI presents a command for bank 7. Bank 7 has not been
opened by the PPC440MC DDR2 Memory Controller, the conflict is a real conflict. The PPC440MC
DDR2 Memory Controller closes the least recently used bank (bank 0, which is held in internal_bank3)
and
MCMIADDRREADYTOACCEPT signal to service the conflict.
X-Ref Target - Figure 13
MCMIADDRREADYTOACCEPT
Figure
MIMCREADNOTWRITE
MIMCBANKCONFLICT/
MIMCADDRESSVALID
opens
MIMCROWCONFLICT
internal_auto_ref_flag
13, the PPC440MC DDR2 Memory Controller has four banks open in clock 1. The MCI
MIMCADDRESS
internal_conflict
cmd_to_DDR2
internal_bank0
internal_bank1
internal_bank2
internal_bank3
mi_mc_clk
bank
Figure 13: Bank Management with Four Internal Banks Open
7.
1
The
2
B4,R1
B1,R1
B0,R0
B3,R0
B0,R0
PPC440MC
www.xilinx.com
8
B0,R0
B4,R1
B1,R1
B3,R0
B1,R1
Wr,B0
DDR2 Memory Controller for PowerPC 440 Processors
DDR2
15
B1,R1
B0,R0
B4,R1
B3,R0
B3,R0
Wr,B1
Memory
22
Controller
B3,R0
B1,R1
B0,R0
B4,R1
Wr,B3
B4,R1
also
29
B7,R1
Wr,B4
B4,R1
B3,R0
B1,R1
B0,R0
deasserts
Pre,B0
DS567_14_071607
Act,B7
B7, R1
B4, R1
B3, R0
B1, R1
the
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