DS567 XILINX [Xilinx, Inc], DS567 Datasheet - Page 5

• Manufacturer Part Number: DS567
• Description: DDR2 Memory Controller for PowerPC 440 Processors
• Manufacturer: XILINX [Xilinx, Inc]

DS567 (v1.1.1) March 31, 2008
Table 2: PPC440MC DDR2 Memory Controller Design Parameters (Cont’d)
Notes:
1.
2.
3.
4.
5.
6.
Delay after ACTIVE command before
PRECHARGE command (ps)
Delay after PRECHARGE command
(ps)
Delay after AUTOREFRESH before
another command (ps)
Read to PRECHARGE command
delay (ps)
Write Recovery Time (ps)
Write-to-Read Command Delay (ps)
Average periodic refresh command
interval (ns)
Skip 200 µs power up delay for
simulation
IDELAY high-performance mode
log
log
log
Optional pipeline stage in read
data path
I/O column location of DQS groups
Master/Slave location of DQ I/O
Number of IDELAYCTRLs required
(log
2
2
2
2
– MCI burst width of 32 for DDR2 data width of 16
– MCI burst width of 64 for DDR2 data width of 32
– MCI burst width of 128 for DDR2 data width of 64
When the parameter C_DDR_CAS_LAT is set to 3, the user must set the C_DDR2_ADDT_LAT parameter to any
value from 1 to 4.
– MCI burst length of 2 for DDR2 burst length of 4
– MCI burst length of 4 for DDR2 burst length of 8
C_DQS_IO_COL is always be 16'd0 because the PPC440MC interfaces use the left column banks.
If the optimal UCF provided in the pcore directory is not used and DQS and DQ bits are not placed in the banks
recommended in the optimal UCF then a PERL script (ftp://ftp.xilinx.com/pub/applications/misc/ar29313.zip) must
be used to determine the correct values of C_DQS_IO_COL and C_DQ_IO_MS. This script requires the user UCF
as its input. The PERL script outputs a UCF and a text file. The contents of the output UCF with additional
constraints for DQS and DQ must be appended to the user UCF. The text file with the correct values of
C_DQS_IO_COL and C_DQ_IO_MS must be copied to the .mhs file. The value for C_DQ_IO_MS depends on DQ
pin allocation.
The C_NUM_IDELAYCTRL parameter affects the number of instantiations of the IDELAYCTRL primitive in the RTL
code. This parameter value has to be set to 1, 2, or 3 depending on the number of FPGA banks used for DQS/DQ
signals. For example, if there are three FPGA banks being used to place DQS/DQ signals for a 64-bit memory
interface then this parameter C_NUM_IDELAYCTRL equals 3. The location constraints of the IDELAYCTRL
primitives have to be set in the UCF. The location coordinates for the IDELAYCTRL primitive depend on the FPGA
bank being used and can be determined using FPGA editor. The optimal UCFs provided in the pcore directory
already have the location constraints for the IDELAYCTRL primitives.
of C_DQS_WIDTH
of C_DDR_DWIDTH
of C_NUM_RANKS_MEM
of C_DQS_WIDTH)
Feature/Description
C_DDR_TRAS
C_DDR_TRP
C_DDR_TRFC
C_DDR_TRTP
C_DDR_TWR
C_DDR_TWTR
C_DDR_TREFI
C_SIM_ONLY
C_IDEL_HIGH_PERF
C_DQS_BITS
C_DQ_BITS
C_CS_BITS
C_READ_DATA_PIPELINE
C_DQS_IO_COL
C_DQ_IO_MS
C_NUM_IDELAYCTRL
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Parameter Name
DDR2 Memory Controller for PowerPC 440 Processors
(5)
(4)(5)
(6)
0, 1
TRUE, FALSE
—
—
—
0 or 1
See
See
1, 2, 3
Table 3
Table 3
Allowable Values
40000
15000
70000
7500
15000
10000
7800
0
TRUE
0
0
Default
Value
5