SSTUB32866EC/S NXP [NXP Semiconductors], SSTUB32866EC/S Datasheet
SSTUB32866EC/S
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SSTUB32866EC/S Summary of contents
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SSTUB32866 1.8 V 25-bit 14-bit configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 04 — 15 April 2010 1. General description The SSTUB32866 is a 1.8 V configurable register specifically designed ...
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... SSTUB32866EC/S Pb-free (SnAgCu solder ball compound) 4.1 Ordering options Table 2. Type number SSTUB32866EC/G SSTUB32866EC/S SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity Package Name Description LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 × 5.5 × 1.05 mm LFBGA96 plastic low profile fine-pitch ball grid array package ...
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NXP Semiconductors 5. Functional diagram (1) Disabled configuration. Fig 1. SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity RESET CK CK VREF DCKE DODT DCS CSR other channels (D3, ...
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NXP Semiconductors RESET CK CK D2, D3, D5, D6 D14 VREF C1 PAR_IN C0 Fig 2. Parity logic diagram for Register A configuration (positive logic SSTUB32866_4 Product data ...
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... D21 N D11 D22 P D12 D23 R D13 D24 T D14 D25 Ball mapping register ( All information provided in this document is subject to legal disclaimers. Rev. 04 — 15 April 2010 SSTUB32866 SSTUB32866EC/G SSTUB32866EC 002aac011 Transparent top view 3 ...
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NXP Semiconductors Fig 5. Fig 6. SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity DCKE PPO B D2 DNU C D3 DNU D DODT QERR n.c. G PAR_IN ...
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NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin GND B3, B4, D3, D4, F3, F4, H3, H4, K3, K4, M3, M4, P3 A4, C3, C4, E3, E4, DD G3, G4, J3, J4, L3, L4, N3, ...
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NXP Semiconductors [3] Data outputs = Q2, Q3, Q5, Q6 Q25 when and Data outputs = Q2, Q3, Q5, Q6 Q14 when and Data ...
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NXP Semiconductors The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states when both DCS and CSR inputs are HIGH. If either ...
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NXP Semiconductors Table 5. Parity and standby function table L = LOW voltage level HIGH voltage level don’t care; RESET DCS CSR ...
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... PAR_IN inputs 0.65 × V [1] RESET, Cn [1] RESET [2] CK, CK 0.675 [2] CK, CK 600 - - operating in free air SSTUB32866EC/G 0 SSTUB32866EC/S 0 All information provided in this document is subject to legal disclaimers. Rev. 04 — 15 April 2010 SSTUB32866 Typ Max - 2.0 0.50 × V 0.51 × − 0.040 0.040 ref ref ...
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NXP Semiconductors 10. Characteristics Table 8. Characteristics At recommended operating conditions (see Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I supply current DD I dynamic operating current DDD per MHz C ...
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NXP Semiconductors Table 9. Timing requirements At recommended operating conditions (see Symbol Parameter f clock frequency clock t pulse width W t differential inputs active time ACT t differential inputs inactive time INACT t set-up time su t hold time ...
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NXP Semiconductors 10.1 Timing diagrams RESET DCS CSR D25 Q25 PAR_IN PPO QERR Fig 7. Timing diagram for SSTUB32866 used as a single device SSTUB32866_4 ...
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NXP Semiconductors RESET DCS CSR D14 Q14 PAR_IN PPO QERR (not used) Fig 8. Timing diagram for the first SSTUB32866 ( Register A configuration) device used in pair; C0 ...
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NXP Semiconductors RESET DCS CSR D14 Q1 to Q14 (1) PAR_IN PPO (not used) QERR (1) PAR_IN is driven from PPO of the first SSTUB32866 device. Fig 9. Timing diagram for the second SSTUB32866 (1 : ...
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NXP Semiconductors 11. Test information 11.1 Parameter measurement information for data output load circuit = 1.8 V ± 0 All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z The outputs ...
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NXP Semiconductors Fig 13. Voltage waveforms; set-up and hold times Fig 14. Voltage waveforms; propagation delay times (clock to output) Fig 15. Voltage waveforms; propagation delay times (reset to output) SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer ...
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NXP Semiconductors 11.2 Data output slew rate measurement information = 1.8 V ± 0 All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z (1) C Fig 16. Load circuit, HIGH-to-LOW ...
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NXP Semiconductors 11.3 Error output load circuit and voltage measurement information = 1.8 V ± 0 All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z (1) C Fig 20. Load ...
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NXP Semiconductors Fig 23. Voltage waveforms, open-drain output LOW to HIGH transition time with respect 11.4 Partial parity out load circuit and voltage measurement information = 1.8 V ± 0 All input pulses are supplied by generators ...
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NXP Semiconductors Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with parity LVCMOS RESET output and t are ...
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NXP Semiconductors 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm ball A1 index area ...
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NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to ...
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NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 14. Acronym CMOS DDR DIMM LVCMOS PPO PRR RDIMM SSTL ...
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NXP Semiconductors 15. Revision history Table 15. Revision history Document ID Release date SSTUB32866_4 20100415 • Modifications: Section 1 “General • Table 8 SSTUB32866_3 20070423 SSTUB32866_2 20061009 SSTUB32866_1 20060518 SSTUB32866_4 Product data sheet 1.8 V DDR2-800 configurable registered buffer with ...
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NXP Semiconductors 16. Legal information 16.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors ...
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NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...