SSTUB32866EC/S NXP [NXP Semiconductors], SSTUB32866EC/S Datasheet - Page 4
SSTUB32866EC/S
Manufacturer Part Number
SSTUB32866EC/S
Description
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.SSTUB32866ECS.pdf
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NXP Semiconductors
SSTUB32866_4
Product data sheet
Fig 2.
D2, D3, D5, D6,
Parity logic diagram for 1 : 2 Register A configuration (positive logic); C0 = 0, C1 = 1
D8 to D14
PAR_IN
RESET
VREF
CK
CK
C1
C0
11
D2, D3, D5, D6,
R
COUNTER
(internal node)
CLK
2-BIT
All information provided in this document is subject to legal disclaimers.
D8 to D14
D
R
D
R
LPS0
CLK
CLK
CE
PARITY
CHECK
Rev. 04 — 15 April 2010
11
0
1
1.8 V DDR2-800 configurable registered buffer with parity
(internal node)
LPS1
D
R
CLK
CE
11
D2, D3, D5, D6,
D8 to D14
D
R
CLK
D
R
CLK
0
1
1
0
SSTUB32866
002aaa650
11
11
© NXP B.V. 2010. All rights reserved.
Q2A, Q3A,
Q5A, Q6A,
Q8A to Q14A
Q2B, Q3B,
Q5B, Q6B,
Q8B to Q14B
PPO
QERR
4 of 30
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