SSTUB32866EC/S NXP [NXP Semiconductors], SSTUB32866EC/S Datasheet - Page 17

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SSTUB32866EC/S

Manufacturer Part Number
SSTUB32866EC/S
Description
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
11. Test information
SSTUB32866_4
Product data sheet
11.1 Parameter measurement information for data output load circuit
V
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z
The outputs are measured one at a time with one transition per measurement.
Fig 10. Load circuit, data output measurements
Fig 11. Voltage and current waveforms; inputs active and inactive times
Fig 12. Voltage waveforms; pulse duration
DD
= 1.8 V ± 0.1 V.
(1) C
(1) I
CK inputs
V
V
V
DD
L
ID
IH
IL
includes probe and jig capacitance.
= V
tested with clock and data inputs held at V
= 600 mV.
= V
ref
ref
All information provided in this document is subject to legal disclaimers.
R L = 100 Ω
test point
− 250 mV (AC voltage levels) for differential inputs. V
test point
+ 250 mV (AC voltage levels) for differential inputs. V
o
RESET
= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
input
LVCMOS
50 Ω
Rev. 04 — 15 April 2010
I
DD
1.8 V DDR2-800 configurable registered buffer with parity
(1)
0.5V
t
INACT
DD
V
10 %
ICR
CK
CK
DUT
OUT
t
W
DD
or GND, and I
delay = 350 ps
Z o = 50 Ω
0.5V
V
ICR
t
ACT
DD
IL
O
IH
C L = 30 pF (1)
= GND for LVCMOS inputs.
= 0 mA.
SSTUB32866
= V
002aaa373
V
0 V
DD
V
DD
002aaa372
ID
90 %
V
V
for LVCMOS inputs.
IH
IL
© NXP B.V. 2010. All rights reserved.
V
DD
R L = 1000 Ω
R L = 1000 Ω
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