SSTUB32866EC/S NXP [NXP Semiconductors], SSTUB32866EC/S Datasheet - Page 5

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SSTUB32866EC/S

Manufacturer Part Number
SSTUB32866EC/S
Description
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
6. Pinning information
SSTUB32866_4
Product data sheet
6.1 Pinning
Fig 3.
Fig 4.
Pin configuration for LFBGA96
Ball mapping, 1 : 1 register (C0 = 0, C1 = 0)
All information provided in this document is subject to legal disclaimers.
G
M
A
B
C
D
E
F
H
K
N
P
R
T
J
L
Rev. 04 — 15 April 2010
PAR_IN
DODT
DCKE
D10
D11
D12
D13
D14
D2
D3
D5
D6
CK
CK
D8
D9
1
1.8 V DDR2-800 configurable registered buffer with parity
RESET
QERR
PPO
DCS
CSR
ball A1
index area
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
2
M
D
H
B
F
K
P
T
G
A
C
E
N
R
J
L
SSTUB32866EC/G
SSTUB32866EC/S
VREF
VREF
Transparent top view
GND
GND
GND
GND
GND
GND
GND
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
3
1
2
3
002aac011
GND
GND
GND
GND
GND
GND
GND
V
V
V
V
V
V
V
V
V
4
4
DD
DD
DD
DD
DD
DD
DD
DD
DD
5
6
QODT
QCKE
QCS
Q10
Q11
Q12
Q13
Q14
n.c.
Q2
Q3
Q5
Q6
C1
Q8
Q9
5
002aab108
SSTUB32866
DNU
DNU
DNU
Q15
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
Q24
Q25
n.c.
C0
6
© NXP B.V. 2010. All rights reserved.
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