SSTUG32866EC/G NXP [NXP Semiconductors], SSTUG32866EC/G Datasheet - Page 17

• Manufacturer Part Number: SSTUG32866EC/G
• Description: 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
11. Test information
SSTUG32866_1
Product data sheet
11.1 Parameter measurement information for data output load circuit
V
All input pulses are supplied by generators having the following characteristics:
PRR
The outputs are measured one at a time with one transition per measurement.
Fig 10. Load circuit, data output measurements
Fig 11. Voltage and current waveforms; inputs active and inactive times
Fig 12. Voltage waveforms; pulse duration
DD
= 1.8 V
(1) C
(1) I
CK inputs
10 MHz; Z
V
V
V
DD
ID
IH
IL
L
includes probe and jig capacitance.
= V
tested with clock and data inputs held at V
= 600 mV.
= V
ref
0.1 V.
ref
+ 250 mV (AC voltage levels) for differential inputs. V
R L = 100
test point
test point
o
250 mV (AC voltage levels) for differential inputs. V
RESET
= 50 ; input slew rate = 1 V/ns
input
LVCMOS
50
Rev. 01 — 29 June 2007
I
DD
(1)
1.8 V DDR2-1G configurable registered buffer with parity
0.5V
t
INACT
DD
V
10 %
ICR
CK
CK
DUT
OUT
t
W
DD
or GND, and I
20 %, unless otherwise specified.
delay = 350 ps
Z o = 50
0.5V
V
ICR
t
IL
IH
ACT
O
DD
= GND for LVCMOS inputs.
= 0 mA.
= V
C L = 30 pF (1)
SSTUG32866
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V
0 V
DD
DD
V
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ID
for LVCMOS inputs.
90 %
V
V
IH
IL
© NXP B.V. 2007. All rights reserved.
V
DD
R L = 1000
R L = 1000
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