SSTUG32866EC/G NXP [NXP Semiconductors], SSTUG32866EC/G Datasheet - Page 4

• Manufacturer Part Number: SSTUG32866EC/G
• Description: 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SSTUG32866_1
Product data sheet
Fig 2. Parity logic diagram for 1 : 2 Register A configuration (positive logic); C0 = 0, C1 = 1
D2, D3, D5, D6,
D8 to D14
PAR_IN
RESET
VREF
CK
CK
C1
C0
11
D2, D3, D5, D6,
R
COUNTER
(internal node)
CLK
2-BIT
D8 to D14
D
R
D
R
LPS0
CLK
CLK
CE
PARITY
CHECK
Rev. 01 — 29 June 2007
11
0
1
1.8 V DDR2-1G configurable registered buffer with parity
(internal node)
LPS1
D
R
CLK
CE
11
D2, D3, D5, D6,
D8 to D14
D
R
CLK
D
R
CLK
0
1
1
0
SSTUG32866
002aaa650
11
11
© NXP B.V. 2007. All rights reserved.
Q2A, Q3A,
Q5A, Q6A,
Q8A to Q14A
Q2B, Q3B,
Q5B, Q6B,
Q8B to Q14B
PPO
QERR
4 of 28