SSTUG32866EC/G NXP [NXP Semiconductors], SSTUG32866EC/G Datasheet - Page 20

• Manufacturer Part Number: SSTUG32866EC/G
• Description: 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SSTUG32866_1
Product data sheet
11.3 Error output load circuit and voltage measurement information
V
All input pulses are supplied by generators having the following characteristics:
PRR
Fig 20. Load circuit, error output measurements
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
Fig 22. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
DD
= 1.8 V
(1) C
10 MHz; Z
RESET input.
to clock inputs
L
includes probe and jig capacitance.
0.1 V.
o
waveform 1
= 50 ; input slew rate = 1 V/ns
waveform 2
RESET
output
timing
inputs
output
Rev. 01 — 29 June 2007
LVCMOS
1.8 V DDR2-1G configurable registered buffer with parity
t
DUT
PLH
OUT
V
t
HL
0.5V
ICR
0.15 V
DD
0.5V
DD
C
L
= 10 pF
V
ICR
(1)
20 %, unless otherwise specified.
V
DD
R
test point
002aaa500
L
002aaa502
= 1 k
SSTUG32866
002aaa501
V
V
V
V
0 V
V
0 V
DD
OL
i(p-p)
DD
OH
© NXP B.V. 2007. All rights reserved.
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