HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 283

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

14.4 CPU Interrupts and DTC Interrupts
The SCI can request three types of interrupts: transmit-end (TXI), receive-end (RXI), and
receive-error (ERI). Interrupt requests are enabled or disabled by the TIE and RIE bits in the
SCR. Independent signals are sent to the interrupt controller for each type of interrupt. The
transmit-end and receive-end interrupt request signals are obtained from the TDRE and RDRF
flags. The receive-error interrupt request signal is the logical OR of the three error flags: overrun
error (ORER), framing error (FER), and parity error (PER). Table 14-9 lists information about
these interrupts.
If the last bit of the next byte is received while the RDRF bit is still set to 1, an overrun error
occurs. The error is handled as described under “Data Reception” above. The overrun error
does not affect the transmit section of the SCI, which continues to transmit normally.
(5) First, the transmit data are transferred from the TDR to the TSR. This makes the TDR
(6) In the receiving section, when 8 bits of data have been received they are transferred from
(7) To clear the RDRF bit software read the RDRF bit in the SSR, read the data in the RDR,
empty, so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt
(TXI) is requested.
If continuous data transmission is desired, the CPU must read the TDRE bit in the SSR,
write the next transmit data in the TDR, then clear the TDRE bit to 0. Alternatively, the
DTC can write the next transmit data in the TDR, in which case the TDRE bit is cleared
automatically.
If the TDRE bit is not cleared to 0 by the time the SCI finishes sending the current byte
from the TSR, the TXD pin continues to output the last bit in the TSR.
the RSR to the RDR and the RDRF bit in the SSR is set to 1. If the RIE bit is set to 1, a
receive-end interrupt (RXI) is requested.
then write a 0 in the RDRF bit. Alternatively, the DTC can read the RDR, in which case
the RDRF bit is cleared automatically.
For continuous data reception, the RDRF bit must be cleared to 0 before the last bit of
the next byte of data is received.
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