HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 69

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

3.5 Instruction Set
3.5.1 Overview
The main features of the CPU instruction set are:
• A general-register architecture.
• Orthogonality. Addressing modes and data sizes can be specified independently in each instruction.
• 1.5 addressing modes (supporting register-register and register-memory operations)
• Affinity for high-level languages, particularly C, with short formats for frequently-used
• Standard mnemonics, common throughout the H Series.
The CPU instruction set includes 63 types of instructions, listed by function in table 3-9.
Table 3-9 Instruction Classification
Function
Data transfer
Arithmetic operations
Logic operations
Shift
Bit manipulation
Branch
System control
* Bcc is a conditional branch instruction in which cc represents a condition code.
Tables 3-10 to 3-16 give a concise summary of the instructions in each functional category. The
MOV, ADD, and CMP instructions have special short formats, which are listed in table 3-17. For
detailed descriptions of the instructions, refer to the H8/500 Series Programming Manual.
The notation used in tables 3-10 to 3-17 is defined below.
instructions and addressing modes.
Instructions
MOV, LDM, STM, XCH, SWAP, MOVTPE, MOVFPE
ADD, SUB, ADDS, SUBS, ADDX, SUBX, DADD, DSUB,
MULXU, DIVXU, CMP, EXTS, EXTU, TST, NEG, CLR,
TAS
AND, OR, XOR, NOT
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
BSET, BCLR, BTST, BNOT
Bcc*, JMP, PJMP, BSR, JSR, PJSR, RTS, PRTD,
PRTS, RTD, SCB (/F, /NE, /EQ)
TRAPA, TRAP/VS, RTE, SLEEP, LDC, STC, ANDC,
ORC, XORC, NOP, LINK, UNLK
50
Total
Types
7
17
4
8
4
11
12
63