HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 367

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

A.4 Instruction Execution Cycles
Tables A-7 (1) through (6) list the number of cycles required by the CPU to execute each
instruction in each addressing mode.
The meaning of the symbols in the tables is explained below. The values of I, J, and K are used to
calculate the number of execution cycles when off-chip memory is accessed for an instruction
fetch or operand read/write. The formulas for these calculations are given next.
A.4.1 Calculation of Instruction Execution States
Instruction Fetch
On-chip memory
Off-chip memory
Notes: *1. When the instruction is fetched from on-chip memory (ROM or RAM), the number of
*2. If wait states are inserted in access to external memory, add the necessary number of
execution states varies by 1 or 2 depending of whether the instruction is stored at an
even or odd address. This difference must be noted when software is used for timing,
and in other cases in which the exact number of states is important.
cycles.
*1
*2
Operand Read/Write
On-chip memory
On-chip memory module
or off-chip memory
On-chip memory
On-chip supporting module
or off-chip memory
*2
*2
358
(Value in table A-8)
Word
Word
Number of States
(Value given in table A-7) +
Byte
(Value given in table A-7) + 2(J + K)
Byte
(Value in table A-7) +
(Value in table A-8) + I
((Value in table A-7) +
(Value in table A-8) + 2I
(Value in table A-7) +
I + 2(J + K)
((Value in table A-7) +
2(I + J + K)