DM9601E ETC1 [List of Unclassifed Manufacturers], DM9601E Datasheet - Page 19

• Manufacturer Part Number: DM9601E
• Description: USB Ethernet MAC Controller with Intergrated 10/100 PHY
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where：
<Reset Value>:
10.1 Network Control Register (00H)
10.2 Network Status Register (01H)
Final
Version: DM9601-DS-F01
June 22, 2002
1
0
X
Bit
2:1
Bit
7
6
5
4
3
0
7
6
5
4
3
2
1
0
RESERVED
WAKEST
TX2END
TX1END
TXFULL
EXT_PHY
LINKST
RXRDY
SPEED
WAKEEN
RXOV
Name
Name
FCOL
Bit set to logic one
Bit set to logic zero
No default value
FDX
RST
LBK
0,RW/C1
0,RW/C1
0,RW/C1
Default
X,RO
X,RO
0,RO
0,RO
0,RO
Default
00,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RO
Select External PHY When Set
Force Collision Mode, used for testing.
Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode
Loopback Mode
Link status 0:link failed 1:link OK, when internal PHY is used
TX Packet 2 Complete Status
TX Packet 1 Complete Status
RX Packet Ready, there are one or more packets in RX FIFO
When clear select Internal PHY. This bit will not be affected after a software reset
Wakeup Event Enable
When set, it enables the wakeup function. Clearing this bit will also clear all wakeup
event status.
This bit will not be affected after a software reset.
Reserved
Bit 2 1
Software reset and auto clear after 10us
Media speed 0:100Mbps 1:10Mbps, when internal PHY is used. This bit is no
meaning when LINKST=0
Wakeup Event Status
Clears by read or write 1. This bit will not be affected after a software reset
TX FIFO Full
When there are two packets in TX SRAM, TX FIFO FULL will be set
Clears by read or write 1.Transmit completion of packet index 2
Clears by read or write 1. Transmit completion of packet index 1
RX FIFO Overflow
0
0
1
1
0
1
0
1
USB to Ethernet MAC Controller with Integrated 10/100 PHY
normal
MAC internal loopback
internal PHY digital loopback
internal PHY analog loopback
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
Description
Description
DM9601
19