DM9601E ETC1 [List of Unclassifed Manufacturers], DM9601E Datasheet - Page 23

• Manufacturer Part Number: DM9601E
• Description: USB Ethernet MAC Controller with Intergrated 10/100 PHY
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

10.11 RX/TX Flow Control Register ( 0AH )
10.12 EEPROM & PHY Control Register ( 0BH )
10.13 EEPROM & PHY Address Register ( 0CH )
10.14 EEPROM & PHY Data Register ( EE_PHY_L： ： ： ： 0DH
Final
Version: DM9601-DS-F01
June 22, 2002
Bit
7:0
7:0
7:6
7:6
5:0
Bit
Bit
Bit
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Name
RESERVED
PHY_ADR
EE_PHY_H
EE_PHY_L
ERPRW
ERPRR
EROA
Name
Name
REEP
EPOS
ERRE
RXPCS
TXPEN
WEP
BKPM
Name
BKPA
RXPS
TXP0
TXPF
FLCE
Default
Default
Default
Default
1,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RO
0,RO
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,R/C
0,RO
X,RW
X,RW
TX pause packet, Auto clears after pause packet transmission completion.
Set to TX pause packet with time = 0000H
TX pause packet, Auto clears after pause packet transmission completion.
Set to TX pause packet with time = FFFFH.
Force TX Pause Packet Enable
Enable the pause packet for high/low water threshold control.
Back pressure mode. This mode is for half duplex mode only. Generates a jam
pattern when any packet coming and RX SRAM over BPHW.
pattern when a packet’s DA match and RX SRAM over BPHW.
RX pause packet status, latch and read clear
RX pause packet current status
Flow Control Enable
Set to enable the flow control mode(i.e. to disable TX function).
Back pressure mode. This mode is for half duplex mode only. Generates a jam
Reserved
Reload EEPROM. Driver needs to clear it after operation complete.
Write EEPROM enable
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY.
EEPROM Read or PHY Register Read Command. Driver needs to clear it after
operation complete.
EEPROM Write or PHY Register Write Command. Driver needs to clear it after
operation complete.
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress.
PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 if
internal PHY is selected
EEPROM Word Address or PHY Register Address
Description
EEPROM or PHY Low Byte Data
EEPROM or PHY High Byte Data
USB to Ethernet MAC Controller with Integrated 10/100 PHY
EE_PHY_H： ： ： ： 0EH )
Description
Description
Description
DM9601
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