DM9601E ETC1 [List of Unclassifed Manufacturers], DM9601E Datasheet - Page 35

• Manufacturer Part Number: DM9601E
• Description: USB Ethernet MAC Controller with Intergrated 10/100 PHY
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

11.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Preliminary
Version: DM9601-DS-P01
June 22, 2001
17.15
17.14
17.13
17.12
16.6
16.5
16.4
16.3
16.2
16.1
16.0
Bit
RPDCTR-EN
RESERVED
RESERVED
Bit Name
100HDX
100FDX
SMRST
MFPSC
RLOUT
SLEEP
10HDX
10FDX
Default
1, RW
0, RW
0, RW
0, RW
0, RW
1, RO
1, RO
1, RO
1, RO
0, RO
0, RO
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M full duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M half duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 10M Full Duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode.
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
Reserved
Write as 0, ignore on read
Reserved
Write as 0, ignore on read
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 : Disable automatic reduced power down
1 : Enable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loopout Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Description
DM9601
35