DM9601E ETC1 [List of Unclassifed Manufacturers], DM9601E Datasheet - Page 36

• Manufacturer Part Number: DM9601E
• Description: USB Ethernet MAC Controller with Intergrated 10/100 PHY
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

36
17.8-17.4
17.3-17.0
17.11-
17.9
PHYADR[4:0]
RESERVED
ANMB[3:0]
(PHYADR),
0, RO
0, RO
RW
If this bit is 1, it means the operation 1 mode is a 10M half duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
Reserved
Write as 0, ignore on read
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple
PHY entities must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
written to these bits
USB to Ethernet MAC Controller with Integrated 10/100 PHY
B3 b2 b1 B0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
Auto-negotiation completed successfully
Version: DM9601-DS-F01
DM9601
June 22, 2002
Final