W9751G6KB WINBOND [Winbond], W9751G6KB Datasheet - Page 12

• Manufacturer Part Number: W9751G6KB
• Description: 8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
• Manufacturer: WINBOND [Winbond]

7.2.2.2
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization,
and upon returning to normal operation after having the DLL disabled. The DLL is automatically
disabled when entering Self Refresh operation and is automatically re-enabled and reset upon exit of
Self Refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must
occur before a Read command can be issued to allow time for the internal clock to be synchronized
with the external clock. Failing to wait for synchronization to occur may result in a violation of the t
or t
Notes:
1. A11 default is “0” RDQS disabled.
2. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066.
3. When Adjust mode is issued, AL from previously set value must be applied.
4. After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. Refer to the section 7.2.3 for
5. Output disabled - DQs, LDQS, LDQS , UDQS, UDQS . This feature is used in conjunction with DIMM I
detailed information.
when I
DQSCK
A12
A10
0
1
0
1
BA1 BA0
DDQ
0
0
1
1
A9
DLL Enable/Disable
0
0
0
1
1
Output buffer enabled
Output buffer disabled
parameters.
Driver impedance adjustment
BA1
is not desired to be included.
Enable
Disable
Qoff (Optional)*
DQS
0
1
0
1
0
A8
0
0
1
0
1
BA0 A12
1
MRS mode
A7
EMR (1)
EMR (2)
EMR (3)
0
1
0
0
1
MR
Qoff
OCD Calibration Program
OCD calibration mode exit; matain setting
Drive (1)
Drive (0)
Adjust mode*
OCD Calibration default*
5
(DQS Enable)
0 (Enable)
1 (Disable)
A11 A10
0*
A10
1
DQS
3
Strobe Function Matrix
A9
OCD program
DQS
DQS
DQS
4
A8
Figure 3 – EMR (1)
A6
0
0
1
1
A7
DQS
DQS
Hi-z
A2
0
1
0
1
A6
Rtt
ODT Disabled
- 12 -
Rtt (nominal)
150 ohm
75 ohm
50 ohm*
Additive Latency
A5
A1
0
1
Output Driver Impedance Control
2
A4
WR
A5
impedance control
0
0
0
0
1
1
1
1
Output driver
Reduced
Normal
A3
A4
BT
0
0
1
1
0
0
1
1
Publication Release Date: Dec. 09, 2011
Additive Latency
A2
A3
Rtt D.I.C DLL
A0
0
1
0
1
0
1
0
1
0
1
Reserved
A1
DLL Enable
Latency
Driver
100%
60%
Disable
size
Enable
0
1
2
3
4
5
6
A0
W9751G6KB
Extended Mode Register (1)
Address Field
DD
measurements
Revision A01
AC