W9751G6KB WINBOND [Winbond], W9751G6KB Datasheet - Page 13

• Manufacturer Part Number: W9751G6KB
• Description: 8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
• Manufacturer: WINBOND [Winbond]

7.2.2.3
( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "H", A0 to A12 = Register data)
The extended mode register (2) controls refresh related features. The default value of the extended
mode register (2) is not defined, therefore the extended mode register (2) must be programmed during
initialization for proper operation.
The DDR2 SDRAM should be in all bank precharge state with CKE already high prior to writing into
the extended mode register (2). The mode register set command cycle time (t
complete the write operation to the extended mode register (2). Mode register contents can be
changed using the same command and clock cycle requirements during normal operation as long as
all banks are in the precharge state.
Notes:
1. The rest bits in EMR (2) is reserved for future use and all bits in EMR (2) except A7, BA0 and BA1 must be programmed to 0
2. When DRAM is operated at 85°C < T
when setting the extended mode register (2) during initialization.
before the Self Refresh mode can be entered.
BA1
BA1
1
0
0
1
1
BA0
BA0
0
1
0
1
Extend Mode Register Set Command (2), EMR (2)
0
A12
MRS mode
EMR (1)
EMR (2)
EMR (3)
MRS
A11
A10
0*
1
A9
CASE
≤ 95°C the extended Self Refresh rate must be enabled by setting bit A7 to "1"
A8
Figure 4 – EMR (2)
SELF
A7
A7
0
1
A6
High Temperature Self Refresh Rate Enable
- 13 -
A5
A4
Enable*
Disable
Publication Release Date: Dec. 09, 2011
0*
2
A3
1
A2
A1
MRD
W9751G6KB
) must be satisfied to
A0
Extended Mode Register (2)
Address Field
Revision A01