W9751G6KB WINBOND [Winbond], W9751G6KB Datasheet - Page 20

• Manufacturer Part Number: W9751G6KB
• Description: 8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
• Manufacturer: WINBOND [Winbond]

7.3
7.3.1
( CS = "L", RAS = "L", CAS = "H", WE = "H", BA0, BA1 = Bank, A0 to A12 be row address)
The Bank Activate command must be applied before any Read or Write operation can be executed.
Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command
on the following clock cycle. If a Read/Write command is issued to a bank that has not satisfied the
t
Read/Write command is internally issued to the device. The additive latency value must be chosen to
assure t
been activated it must be precharged before another Bank Activate command can be applied to the
same bank. The bank active and precharge times are defined as t
minimum time interval between successive Bank Activate commands to the same bank is determined
by the RAS cycle time of the device (t
commands is t
7.3.2
( CS = "L", RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A10 = "L", A0 to A9 = Column
Address)
The READ command is used to initiate a burst read access to an active row. The value on BA0, BA1
inputs selects the bank, and the A0 to A9 address inputs determine the starting column address. The
address input A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected,
the row being accessed will be precharged at the end of the READ burst; if Auto-precharge is not
selected, the row will remain open for subsequent accesses.
RCDmin
Command
Figure 12 – Bank activate command cycle: t
Address
Command Function
Bank Activate Command
Read Command
RCDmin
CLK
CLK
specification, then additive latency must be programmed into the device to delay when the
Row Addr.
RRD
Activate
Bank A
Bank A
T0
is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 and 6 are supported. Once a bank has
RAS - RAS delay time(≥ t
t
.
RCD
= 1
Internal RAS - RAS delay (≥ t
Col. Addr.
Post CAS
T1
Bank A
Bank A
Read
CAS - CAS delay time(t
Additive Latency delay(AL)
Bank Active (≥ t
RRD
Row Addr.
)
Activate
T2
Bank B
Bank B
RCD
RAS
min)
CCD
)
RC
)
Col. Addr.
Post CAS
Bank B
Bank B
T3
). The minimum time interval between Bank Activate
Read
Read Begins
RAS Cycle time (≥ t
- 20 -
RCD
= 3, AL = 2, t
Precharge
Bank A
Bank A
Tn
Addr.
RC
)
Publication Release Date: Dec. 09, 2011
Bank Precharge time (≥ t
Tn+1
RAS
RP
= 3, t
and t
RRD
W9751G6KB
Tn+2
Precharge
Bank B
Bank B
Addr.
RP
RP
, respectively. The
)
= 2, t
CCD
Tn+3
Row Addr.
Activate
Bank A
Bank A
Revision A01
= 2