PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 16
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PSD813F1
Manufacturer Part Number
PSD813F1
Description
Flash In-System Programmable ISP Peripherals For 8-bit MCUs
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.PSD813F1.pdf
(120 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD813F1-A-15J
Manufacturer:
MAXIM
Quantity:
2 500
Table 5.
PSD813F1
Pin
Descriptions
(cont.)
12
PSD813F1-A
Pin Name Pin* Type
PC2
PC3
PC4
PC5
PC6
18
17
14
13
12
I/O
I/O
I/O
I/O
I/O
PC2 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
2. CPLD Micro Cell (McellBC2) output.
3. Input to the PLDs.
4. Vstby — SRAM standby voltage input for SRAM battery
This pin can be configured as a CMOS or Open Drain output.
PC3 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
2. CPLD Micro Cell (McellBC3) output.
3. Input to the PLDs.
4. TSTAT output** for the JTAG interface.
5. Rdy/Bsy output for in-system parallel programming.
This pin can be configured as a CMOS or Open Drain output.
PC4 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
2. CPLD Micro Cell (McellBC4) output.
3. Input to the PLDs.
4. TERR output** for the JTAG interface.
5. Vbaton — battery backup indicator output. Goes high
This pin can be configured as a CMOS or Open Drain output.
PC5 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
2. CPLD Micro Cell (McellBC5) output.
3. Input to the PLDs.
4. TDI input** for the JTAG interface.
This pin can be configured as a CMOS or Open Drain output.
PC6 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
2. CPLD Micro Cell (McellBC6) output.
3. Input to the PLDs.
4. TDO output** for the JTAG interface.
This pin can be configured as a CMOS or Open Drain output.
input port.
backup.
input port.
input port.
when power is being drawn from an external battery.
input port.
input port.
Description
Preliminary