PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 76

• Manufacturer Part Number: PSD813F1
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

72
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
9.5.3 Reset and Power On Requirement
Power On Reset
Upon power up the PSD813F1 requires a reset pulse of tNLNH-PO (minimum 1ms) after
V
of the registers and sets the Flash or EEPROM into operating mode. After the rising edge of
reset, the PSD813F1 remains in the reset state for an additional tOPR (minimum 120 ns)
nanoseconds before the first memory access is allowed.
The PSD813F1 Flash or EEPROM memory is reset to the read array mode upon power up.
The FSi and EESi select signals along with the write strobe signal must be in the false state
during power-up reset for maximum security of the data contents and to remove the possi-
bility of a byte being written on the first edge of a write strobe signal. The PSD
automatically prevents write strobes from reaching the EEPROM memory array for about
5 ms (tEEHWL). Any Flash memory write cycle initiation is prevented automatically when
V
Warm Reset
Once the device is up and running, the device can be reset with a much shorter pulse of
tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
after warm reset. Figure 32 shows the timing of the power on and warm reset.
Figure 32. Power On and Warm Reset Timing
I/O Pin, Register and PLD Status at Reset
Table 33 shows the I/O pin, register and PLD status during power on reset, warm reset and
power down mode. PLD outputs are always valid during warm reset, and they are valid in
power on reset once the internal PSD configuration bits are loaded. This loading of PSD is
completed typically long before the V
active, the state of the outputs are determined by the PSDabel equations.
CC
CC
V
RESET
CC
is steady. During this time period the device loads internal configurations, clears some
is below VLKO.
OPERATING LEVEL
POWER ON RESET
t NLNH – PO
CC
ramps up to operating level. Once the PLD is
t OPR
t NLNH
WARM
RESET
t OPR
Preliminary