PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 97

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PSD813F1

Manufacturer Part Number
PSD813F1
Description
Flash In-System Programmable ISP Peripherals For 8-bit MCUs
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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0
Preliminary
PSD813F1V AC/DC Parameters – CPLD Timing Parameters
(3.0 V to 3.6 V Versions)
CPLD Micro Cell Asynchronous Clock Mode Timing
Input Micro Cell Timing
NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t
*
Symbol
ZPSD Versions Only.
Symbol
t
t
t
t
t
IS
IH
INH
IN L
INO
f
t
t
t
t
t
t
t
MAXA
SA
HA
CHA
CLA
COA
ARD
MINA
*
ZPSD Versions Only.
Maximum Frequency
External Feedback
Maximum Frequency
Internal Feedback ( f
Maximum Frequency
Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
Input Setup Time
Input Hold Time
NIB Input High Time
NIB Input Low Time
NIB Input to Combinatorial
Delay
Parameter
Parameter
(3.0 V to 3.6 V Versions)
CNTA
)
1/(t
Any Micro Cell
1/(t
1/(t
Conditions
S A
1/ f
C H A
S A
+ t
Conditions
C NTA
+ t
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
CO A
+ t
CO A
CLA
–10)
)
)
(3.0 V to 3.6 V Versions)
Min
12
15
22
15
42
Min
25
13
13
0
-15
-15
Max
19.2
23.8
27
40
29
Max
62
Min
13
17
25
16
49
Min
30
15
15
0
-20
-20
Max
16.9
20.4
24.4
46
33
Max
70
Add 4 Add 20
Add 4
Aloc
PT
AVLX
Add 4
Aloc
PT
and t
Add 20
Add 20
Add 20 Sub 6
TURBO
OFF *
LXAX
Add 20
Add 20
TURBO
.
OFF *
Slew
Rate
PSD813F1-A
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
93

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