PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 34

• Manufacturer Part Number: PSD813F1
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

The
PSD813F1
Functional
Blocks
(cont.)
30
PSD813F1-A
Figure 7. Priority Level of Memory and I/O Components
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 8031 and compatible family of microcontrollers, which includes the 80C51, 80C151,
80C251, 80C51XA, and the C500 family, have separate address spaces for code memory
(selected using PSEN) and data memory (selected using RD). Any of the memories within
the PSD813F1 can reside in either space or both spaces. This is controlled through manip-
ulation of the VM register that resides in the PSD’s CSIOP space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, I may wish to have SRAM and Flash in Data Space at boot, and EEPROM in
Program Space at boot, and later swap EEPROM and Flash. This is easily done with
the VM register by using PSDsoft to configure it for boot up and having the microcontroller
change it when desired.
Table 13 describes the VM Register.
NOTE: Bits 6-5 are not used.
Table 13. VM Register
Bit 7
PIO_EN
0 = disable
PIO mode
1= enable
PIO mode
Highest Priority
Lowest Priority
Bit 6* Bit 5*
*
*
*
*
FL_Data EE_Data
0 = RD
access
Flash
1 = RD
Flash
can’t
access
Bit 4
0 = RD
can’t
access
EEPROM
1 = RD
access
EEPROM
Bit 3
EEPROM Memory
SRAM, I/O, or
Peripheral I/O
Flash Memory
Level 1
Level 2
Level 3
FL_Code
0 = PSEN 0 = PSEN
can’t
access
Flash
1 = PSEN 1 = PSEN
access
Flash
Bit 2
can’t
access
EEPROM
access
EEPROM
EE_Code SRAM_Code
Bit 1
0 = PSEN
can’t
access
SRAM
1 = PSEN
access
SRAM
Preliminary
Bit 0