PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 67

• Manufacturer Part Number: PSD813F1
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
9.4.6 Port C – Functionality and Structure
Port C can be configured to perform one or more of the following functions (see Figure 28):
Port C does not support Address Out mode, and therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in certain microcontroller interfaces.
9.4.7 Port D – Functionality and Structure
Port D has three I/O pins. See Figure 29. This port does not support Address Out mode,
and therefore no Control Register is required. Port D can be configured to perform one or
more of the following functions:
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
9.4.7.1 External Chip Select
The CPLD also provides three chip select outputs on Port D pins that can be used to
select external devices. Each chip select (ECS0-2) consists of one product term that can be
configured active high or low. The output enable of the pin is controlled by either the output
enable product term or the Direction Register. (See Figure 29.)
MCU I/O Mode
CPLD Output – McellBC[7:0] outputs can be connected to Port B or Port C.
CPLD Input – via the Input Micro Cells
Address In – Additional high address inputs using the Input Micro Cells.
In-System Programming – JTAG port can be enabled for programming/erase of the
PSD813F1 device. (See Section 9.6 for more information on JTAG programming.)
Open Drain – Port C pins can be configured in Open Drain Mode
Battery Backup features – PC2 can be configured as a Battery Input (Vstby) pin.
MCU I/O Mode
CPLD Output – (external chip select)
CPLD Input – direct input to CPLD, no Input Micro Cells
Slew rate – pins can be set up for fast slew rate
PD0 – ALE, as address strobe input
PD1 – CLKIN, as clock input to the Micro Cells Flip Flops and APD counter
PD2 – CSI, as active low chip select input. A high input will disable the
Flash/EEPROM/SRAM and CSIOP.
PC4 can be configured as a Battery On Indicator output
pin, indicating when Vcc is less than Vbat.
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