M58LT128HSB8ZA6 NUMONYX [Numonyx B.V], M58LT128HSB8ZA6 Datasheet - Page 23

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M58LT128HSB8ZA6

Manufacturer Part Number
M58LT128HSB8ZA6
Description
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet

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M58LT128HST, M58LT128HSB
4.9
Buffer Program command
The Buffer Program Command makes use of the device’s 32-word Write Buffer to accelerate
programming. Up to 32 words can be loaded into the Write Buffer, which can dramatically
reduce in-system programming time compared to the standard non-buffered Program
command.
Four successive steps are required to issue the Buffer Program command:
1.
After the first Bus Write cycle, Read operations in the bank output the contents of the Status
Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 =
‘1’). If the buffer is not available (SR7 = ‘0’), re-issue the Buffer Program command to update
the Status Register contents.
2.
3.
4.
All the addresses used in the Buffer Program operation must lie within the same block.
Invalid address combinations or an incorrect sequence of Bus Write cycles sets an error in
the Status Register and aborts the operation without affecting the data in the memory array.
If the block being programmed is protected an error is set in the Status Register, and the
operation aborts without affecting the data in the memory array.
During Buffer Program operations the bank being programmed only accepts the Read Array,
Read Status Register, Read Electronic Signature, Read CFI Query, and the Program/Erase
Suspend command; all other commands are ignored.
Refer to
about simultaneous operations allowed in banks not being programmed.
See
flowchart on using the Buffer Program command.
Appendix
The first Bus Write cycle sets up the Buffer Program command. The setup code can be
addressed to any location within the targeted block.
The second Bus Write cycle sets up the number of words to be programmed. Value ”n”
is written to the same block address, where n+1 is the number of words to be
programmed.
Use n+1 Bus Write cycles to load the address and data for each word into the Write
Buffer. Addresses must lie within the range from the start address to the start address
+ n, where the start address is the location of the first data to be programmed.
Optimum performance is obtained when the start address corresponds to a 32-word
boundary.
The final Bus Write cycle confirms the Buffer Program command and starts the
program operation.
Chapter 8: Dual operations and multiple bank architecture
C,
Figure 21: Buffer Program flowchart and pseudo code
for detailed information
Command interface
for a suggested
23/110

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