CY14E256L-D45I CYPRESS [Cypress Semiconductor], CY14E256L-D45I Datasheet - Page 10

• Manufacturer Part Number: CY14E256L-D45I
• Description: 256 Kbit (32K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Notes
Document Number: 001-06968 Rev. *G
SRAM Write Cycle
t
t
t
t
t
t
t
t
t
t
12. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
13. HSB must be high during SRAM WRITE cycles.
14. CE or WE must be greater than V
WC
PWE
SCE
SD
HD
AW
SA
HA
HZWE
LZWE
Parameter
Cypress
[11]
[11,12]
ADDRESS
DATA OUT
ADDRESS
DATA OUT
DATA IN
DATA IN
Parameter
WE
CE
CE
WE
t
t
t
t
t
t
t
t
t
t
AVAV
WLWH,
ELWH,
DVWH,
WHDX,
AVWH,
AVWL,
WHAX,
WLQZ
WHQX
t
t
t
t
t
t
t
ELEH
AVEL
AVEH
EHAX
WLEH
DVEH
EHDX
Alt
IH
during address transitions.
PREVIOUS DATA
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
t
SA
Figure 10. SRAM Write Cycle 2: CE Controlled
Figure 9. SRAM Write Cycle 1: WE Controlled
t
SA
Description
HIGH IMPEDANCE
t
t
AW
t
PWE
AW
t
HZWE
t
t
t
SCE
SCE
WC
t
WC
t
t
HIGH IMPEDANCE
PWE
SD
DATA VALID
DATA VALID
Min
t
20
25
20
10
20
SD
0
0
0
5
25 ns
Max
10
[13, 14]
[13, 14]
t
HA
t
t
t
HD
HA
HD
Min
35
25
25
12
25
0
0
0
5
35 ns
t
LZWE
Max
13
Min
45
30
30
15
30
0
0
0
5
CY14E256L
45 ns
Page 10 of 18
Max
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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