CY14E256L-D45I CYPRESS [Cypress Semiconductor], CY14E256L-D45I Datasheet - Page 9

• Manufacturer Part Number: CY14E256L-D45I
• Description: 256 Kbit (32K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

AC Switching Characteristics
SRAM Read Cycle
Switching Waveforms
Notes
Document Number: 001-06968 Rev. *G
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9. WE and HSB must be HIGH during SRAM Read cycles.
10. Device is continuously selected with CE and OE both Low.
11. Measured ±200 mV from steady state output voltage.
ACE
RC
AA
DOE
OHA
LZCE
HZCE
LZOE
HZOE
PU
PD
Parameter
Cypress
[10]
[9]
[8]
[8]
[10]
[11]
[11]
[11]
[11]
Parameter
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t
ELQV
AVAV,
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
t
ELEH
Alt
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Figure 7. SRAM Read Cycle 1: Address Controlled
Figure 8. SRAM Read Cycle 2: CE and OE Controlled
Description
Min
25
0
0
5
5
25 ns
Max
25
10
10
10
25
25
[9, 10]
Min
35
[9]
5
5
0
0
35 ns
Max
35
35
15
13
13
35
Min
45
0
0
5
5
CY14E256L
45 ns
Max
45
45
20
15
15
45
Page 9 of 18
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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