CY14E256LA CYPRESS [Cypress Semiconductor], CY14E256LA Datasheet

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CY14E256LA

Manufacturer Part Number
CY14E256LA
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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256-Kbit (32 K × 8) Nonvolatile SRAM
Features
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-54952 Rev. *F
25 ns and 45 ns access times
Internally organized as 32 K × 8 (CY14E256LA)
Hands-off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or autostore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20-year data retention
Single 5 V +10% operation
Industrial temperature
44-pin thin small-outline package (TSOP II) and 32-pin
small-outline integrated circuit (SOIC) package
Pb-free and restriction of hazardous substances (RoHS)
compliant
198 Champion Court
256-Kbit (32 K × 8) Nonvolatile SRAM
Functional Description
The Cypress CY14E256LA is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is
organized as 32 KB. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
San Jose
,
CA 95134-1709
Revised January 17, 2011
CY14E256LA
408-943-2600
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CY14E256LA Summary of contents

Page 1

... Cypress Semiconductor Corporation Document Number: 001-54952 Rev. *F 256-Kbit (32 K × 8) Nonvolatile SRAM Functional Description The Cypress CY14E256LA is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 32 KB. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory ...

Page 2

... Hardware STORE Cycle ................................................. 14 Truth Table For SRAM Operations ................................ 15 Ordering Information ...................................................... 15 Ordering Code Definition ........................................... 15 Package Diagrams .......................................................... 16 Acronyms ........................................................................ 17 Acronyms Used ......................................................... 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC Solutions ......................................................... 19 CY14E256LA Page [+] Feedback ...

Page 3

... Address expansion for 8 Mbit. NC pin not connected to die. 5. Address expansion for 16 Mbit. NC pin not connected to die. Document Number: 001-54952 Rev. *F [4] [3] [2] [1] [ Description CY14E256LA 32 – SOIC (x8) Top View (not to scale) ) with standard output high HHHD Page [+] Feedback ...

Page 4

... Refer to the Truth Table For SRAM Operations complete description of read and write modes. SRAM Read The CY14E256LA performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A determines which of the 32,768 data bytes each are 0-14 accessed ...

Page 5

... L H Notes 6. While there are 15 address lines on the CY14E256LA, only the lower 14 are used to control software modes. 7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. Document Number: 001-54952 Rev initiate the Software STORE cycle, the following read ...

Page 6

... Output data Output data [7] Output data Active I CC2 Output data Output data Output data Output data Output high Z [7] Output data Active Output data Output data Output data Output data Output high the CY14E256LA write mode Page [+] Feedback ...

Page 7

... V value to make sure there is extra CAP store charge and store time should discuss their V selection with Cypress to understand any impact on the V voltage level at the end period. RECALL CY14E256LA value because CAP charge and CAP value. Customers CAP size ...

Page 8

... Max, V < V < Max, V < V < > OUT – pin and rated CAP SS CY14E256LA + 2 °C)...................................................1.0 W Ambient Temperature V CC –40 °C to +85 °C 4 5.5 V [8] Min Typ Max 4.5 5.0 5.5 – – – – ...

Page 9

... (Typ Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. Figure 3. AC Test Loads 5.0 V OUTPUT 512 Ω CY14E256LA Min Unit 20 Years 1,000 K Max Unit 44-TSOP II 32-SOIC Unit °C/W 41 ...

Page 10

... RC Address Valid t AA Output Data Valid t OHA CY14E256LA 45 ns Unit Max Min Max 25 – – 45 – – – – 3 – ns – 3 – – ...

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... WC Address Valid t SCE PWE Input Data Valid t t LZWE HZWE High Impedance [18, 19, 20 Address Valid SCE t PWE Input Data Valid High Impedance CY14E256LA [17, 18] t HZCE t HZOE Page [+] Feedback ...

Page 12

... Figure 8. AutoStore or Power-up RECALL 22 t Note t STORE HHHD t LZHSB t DELAY t HRECALL Read & Write BROWN POWER-UP OUT RECALL AutoStore SWITCH. is less than V CC SWITCH. CY14E256LA CY14E256LA Unit Min Max – 20 – 8 – 25 – 4.4 150 – – 1.9 – 5 – 500 [25 Note ...

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... Note Figure 10. AutoStore Enable / Disable Cycle t RC Address # HZCE Note Table 1 on page 5. WE must be HIGH during all six consecutive cycles. time. DELAY CY14E256LA Unit Max Min Max – 45 – – 0 – – 30 – – 0 – ...

Page 14

... HSB pin is driven high to V 100 K resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW. t DHSB t DHSB [30, 31] Figure 12. Soft Sequence Processing t Soft Sequence SS Command Address #6 Address # CY14E256LA CY14E256LA Unit Min Max – – ns μs – 100 t HHHD t LZHSB only by Internal ...

Page 15

... Package Type Diagram 51-85127 32-pin SOIC Option: T – Tape and Reel Blank – Std. Temperature: I – Industrial (– Package: ZS – 44 TSOP II SZ – 32 SOIC Data Bus: L – x8 CY14E256LA Mode Power Standby Active Active Active Operating Range Industrial o C) Speed ...

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... SEATING PLANE 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.026[0.660] 0.032[0.812] 0.004[0.101] 0.0100[0.254] CY14E256LA 51-85087 *C MIN. MAX. PART # S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG. 0.006[0.152] 0.021[0.533] 0.012[0.304] 0.041[1.041] 51-85127 *B ...

Page 17

... Document Number: 001-54952 Rev. *F Document Conventions Units of Measure Symbol Unit of Measure Kbit 1024 bits °C degrees celsius KΩ kilo ohms MHz megahertz μA microamperes μf microfarads μs microseconds mA milliampere ms millisecond ns nanoseconds Ω ohms pF picofarads ps picoseconds V volts W watts CY14E256LA Page [+] Feedback ...

Page 18

... Document History Page Document Title: CY14E256LA 256-Kbit (32 K × 8) Nonvolatile SRAM Document Number: 001-54952 Orig. of Revision ECN Change ** 2748216 GVCH/PYRS *A 2772059 GVCH *B 2829117 GVCH *C 2891356 GVCH *D 2922858 GVCH *E 3030490 GVCH *F 3143330 GVCH Document Number: 001-54952 Rev. *F Submission Description of Change Date 08/04/09 New Datasheet ...

Page 19

... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-54952 Rev. *F All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised January 17, 2011 CY14E256LA PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...

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