CY14E256LA CYPRESS [Cypress Semiconductor], CY14E256LA Datasheet - Page 5

• Manufacturer Part Number: CY14E256LA
• Manufacturer: CYPRESS [Cypress Semiconductor]

SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (t
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14E256LA. But any SRAM read and write cycles
are inhibited until HSB is returned HIGH by MPU or other
external source.
During any STORE operation, regardless of how it is initiated,
the CY14E256LA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the nvSRAM memory access is inhibited for
t
unconnected if it is not used.
Hardware RECALL (Power-up)
During power-up or after any low power condition
(V
V
cycle is automatically initiated and takes t
During this time, HSB is driven low by the HSB driver.
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14E256LA Software
STORE cycle is initiated by executing sequential CE or OE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
Table 1. Mode Selection
Document Number: 001-54952 Rev. *F
Notes
LZHSB
6. While there are 15 address lines on the CY14E256LA, only the lower 14 are used to control software modes.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
CC
CC
again exceeds the sense voltage of V
< V
time after HSB pin returns HIGH. Leave the HSB
CE
SWITCH
H
L
L
L
), an internal RECALL request is latched. When
WE
X
H
H
L
DELAY
HRECALL
SWITCH
) to complete before
OE
X
X
L
L
, a RECALL
to complete.
A
0x3C1F
0x0E38
0x31C7
0x03E0
0x303F
0x0B45
14
- A
X
X
X
To initiate the Software STORE cycle, the following read
sequence must be performed:
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the t
activated again for the read and write operation.
Software RECALL
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the t
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0FC0 Initiate STORE cycle
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0C63 Initiate RECALL cycle
0
[6]
Not selected
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Write SRAM
AutoStore
disable
Mode
STORE
RECALL
Output high Z
cycle time is fulfilled, the SRAM is
Output data
Output data
Output data
Output data
Output data
Output data
Output data
cycle time, the SRAM is again
Input data
I/O
CY14E256LA
Standby
Active
Page 5 of 19
Power
Active
Active
[7]
[+] Feedback