CY14E256LA CYPRESS [Cypress Semiconductor], CY14E256LA Datasheet - Page 11

• Manufacturer Part Number: CY14E256LA
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-54952 Rev. *F
Note
17. WE must be HIGH during SRAM read cycles.
18. HSB must remain HIGH during READ and WRITE cycles.
19. If WE is low when CE goes low, the outputs remain in the high impedance state.
20. CE or WE must be > V
Data Output
Data Output
Data Input
Address
Address
Data Output
Data Input
CE
OE
Address
I
WE
CE
CC
WE
IH
CE
during address transitions.
High Impedance
Standby
Figure 5. SRAM Read Cycle #2: CE and OE Controlled
Figure 6. SRAM Write Cycle #1: WE Controlled
Figure 7. SRAM Write Cycle #2: CE Controlled
Previous Data
t
SA
t
PU
t
SA
t
LZCE
t
LZOE
t
Address Valid
AA
t
ACE
High Impedance
t
AW
t
Address Valid
PWE
t
t
t
SCE
HZWE
DOE
t
Address Valid
RC
t
Active
SCE
t
PWE
t
WC
Input Data Valid
t
WC
t
t
SD
High Impedance
SD
Input Data Valid
Output Data Valid
t
LZWE
[18, 19, 20]
[18, 19, 20]
t
HD
t
HD
t
HA
t
HA
[17, 18]
t
t
HZCE
HZOE
t
PD
CY14E256LA
Page 11 of 19
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