HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 36

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

respectively. The minimum time interval between
successive Bank Activate commands to the same bank
is determined (
Bank Active commands, to any other bank, is the Bank
A to Bank B delay time (
In order to ensure that components with 8 internal
memory banks do not exceed the instantaneous
current supplying capability, certain restrictions on
operation of the 8 banks must be observed. There are
two rules.
One for restricting the number of sequential Active
commands that can be issued and another for allowing
Figure 17
2.6
After a bank has been activated, a read or write cycle
can be executed. This is accomplished by setting RAS
high, CS and CAS low at the clock’s rising edge. WE
must also be defined at this time to determine whether
the access cycle is a read operation (WE high) or a
write operation (WE low). The DDR2 SDRAM provides
a wide variety of fast access modes. A single Read or
Write Command will initiate a serial read or write
operation on successive clock cycles at data rates of up
to 667 Mb/sec/pin for main memory. The boundary of
the burst cycle is restricted to specific segments of the
page length.
For example, the 32Mbit
page length of 2048 bits (defined by CA[9:0] & CA11).
Data Sheet
Command
Address
CK, CK
Row Addr.
Bank Activate Command Cycle:
Read and Write Commands and Access Modes
T
0
Bank A
Activate
Bank A
t
RC
Bank A to Bank B delay tRRD.
Internal RAS-CAS delay tRCDmin.
). The minimum time interval between
Posted CAS
Col. Addr.
Read A
T
1
t
Bank A
RRD
tRAS Row Active Time (Bank A)
4 I/O
additive latency AL=2
).
tCCD
Row Addr.
4 Bank chip has a
T
2
Activate
Bank B
Bank B
Posted CAS
Read B
Col. Addr.
T
3
Bank B
Read A Begins
t
RCD
= 3, AL = 2,
36
tRC Row Cycle Time (Bank A)
T
4
more time for RAS precharge for a Precharge-All
command. The rules are as follows:
1. Sequential Bank Activation Restriction (JEDEC
2. Precharge All Allowance:
In case of a 4-bit burst operation (burst length = 4) the
page length of 2048 is divided into 512 uniquely
addressable segments (4-bits
burst operation will occur entirely within one of the 512
segments (defined by CA[8:0] beginning with the
column address supplied to the device during the Read
or Write Command (CA[9:0] & A11). The second, third
and fourth access will also occur within this segment,
however, the burst order is a function of the starting
address, and the burst sequence.
In case of a 8-bit burst operation (burst length = 8) the
page length of 2048 is divided into 256 uniquely
addressable double segments (8-bits
The 8-bit burst operation will occur entirely within one
of the 256 double segments (defined by CA[7:0])
512-Mbit Double-Data-Rate-Two SDRAM
ballot item 1293.15): No more than 4 banks may be
activated in a rolling
clocks is done by deviding
rounding up to next integer value. As an example of
the rolling window, if (
clocks, and an activate command is issued in clock
N, no more than three further activate commands
may be issued in clocks N + 1 through N + 9.
command will equal to
value for a single bank precharge.
HYB18T512[400/800/160]A[C/F]–[3.7/5]
t
RP
Precharge
T
n
Bank A
Bank A
= 3,
Addr.
t
RRD
tRP Row Precharge Time (Bank A)
Tn+1
= 2
NOP
NOP
t
FAW
t
FAW
t
RP
window. Converting to
t
/
Tn+2
Precharge
RP
+ 1
Functional Description
t
t
CK
FAW(ns)
Bank B
Bank B
09112003-SDM9-IQ3P
Addr.
4 I/O each). The 4-bit
) rounds up to 10
for a Precharge-All
t
CK
Rev. 1.13, 2004-05
, where
by
4 I/O each).
Tn+3
Row Addr.
t
CK(ns)
Bank A
Bank A
Activate
t
RP
and
is the
ACT