HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 82

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

9) CL = 3
10) CL = 4 & 5
11) For timing definition, slew rate and slew rate derating see
12) For timing definition, slew rate and slew rate derating see
13) The
14) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
15) The maximum limit for this parameter is not a device limit. The device operate with a greater value for this parameter, but
16)
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The
19) 4 & 8 (1k page size)
20) 16 (2k page size)
21) For each of the terms, if not already an integer, round to the next highest integer.
22)
23) User can choose two different active power-down modes for additional power saving via MRS address bit A12.
24) The Auto-Refresh command interval has be reduced to 3.9
25) 0
26) 85
27) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
Table 41
Symbol
t
t
t
t
t
t
t
t
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in
Data Sheet
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
no longer driving (
valid data transitions.These parameters are verified by design and characterisation, but not subject to production test.
output slew rate mis-match between DQS / DQS and associated DQ in any given cycle.
system performance (bus turnaround) degrades accordingly.
t
equal to 9 x
Therefore a separate parameter
anymore.
WR refers to the WR parameter stored in the MRS.
t
between 85
frequency change during power-down, a specific procedure is required as describes in
max is when the ODT resistance is fully on. Both are measure from
high impedance. Both are measured from
RAS(max)
WTR
o
C - 85
o
C - 95
t
tHZ
is at least two clocks independent of operation frequency.
RCD
,
t
is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down
Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down
Modes)
ODT to Power Down Mode
Entry Latency
ODT Power Down Exit Latency 8
RPST
timing parameter is valid for both activate command to read or write command with and without Auto-Precharge.
o
ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
C
o
o
C
t
C and 95
REFI.
and
t
t
HZ
LZ
,
,
o
t
t
C.
RPST
RPRE
), or begins driving (
parameters are referenced to a specific voltage level, which specify when the device output is
t
RAP
for activate command to read or write command with Auto-Precharge is not necessary
t
AOFD
Min.
2
t
t
2.5
t
t
3
AC(min)
AC(min)
AC(min)
AC(min)
Electrical Characteristics & AC Timing - Absolute Specification
t
.
LZ
,
t
RPRE
+ 2 ns
+ 2 ns
).
82
tHZ
Chapter 8.3
Chapter 8.3
µ
and
s when operating the DDR2 DRAM in a temperature range
512-Mbit Double-Data-Rate-Two SDRAM
t
LZ
HYB18T512[400/800/160]A[C/F]–[3.7/5]
t
transitions occur in the same access time windows as
AOND
Max.
2
t
2
2.5
t
2.5
—
—
.
AC(max)
AC(max)
t
CK
t
CK
+
t
+
t
+ 1 ns
+ 0.6 ns
AC(max)
CK
t
AC(max)
refers to the application clock period.
Chapter
+ 1 ns
+ 1 ns
09112003-SDM9-IQ3P
2.12.
Rev. 1.13, 2004-05
Units
t
ns
ns
t
ns
ns
t
t
CK
CK
CK
CK
Notes
1)
2)