HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 60

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

Power-Down Entry
Active Power-down mode can be entered after an
Activate command. Precharge Power-down mode can
be entered after a Precharge, Precharge-All or internal
precharge command. It is also allowed to enter power-
mode after an Auto-Refresh command or MRS /
EMRS(1) command when
Active Power-down mode entry is prohibited as long as
a Read Burst is in progress, meaning CKE should be
kept high until the burst operation is finished. Therefore
Active Power-Down mode entry after a Read or Read
with Auto-Precharge command is allowed after
RL + BL/2 is satisfied.
Figure 54
Note: Active Power-Down mode exit timing
Figure 55
Note: Active Power-Down mode exit timing t
Data Sheet
D Q S ,
D Q S
C K E
C K , C K
C M D
D Q
state in the MRS, address bit A12.
state in the MRS, address bit A12.
C K E
C K , C K
C M D
R E A D w /A P
T0
R E A D
Active Power-Down Mode Entry and Exit after an Activate Command
Active Power-Down Mode Entry and Exit Example after a Read Command:
RL = 4 (AL = 1, CL =3), BL = 4
T0
A ctivate
AL = 1
T1
Power-Down
N O P
Active
CL = 3
Entry
RL = 4
T1
N O P
tIS
T2
N O P
t
MRD
T2
is satisfied.
N O P
RL + BL/2
T3
N O P
N O P
T4
N O P
Dout A0 Dout A1
t
XARD
XARD
Power-Down
Active
Tn
Exit
T5
(“fast exit”) or
(“fast exit”) or t
N O P
N O P
Dout A2 Dout A3
tIS
60
Tn+1
T6
tXARD or
tXARDS *)
N O P
Active Power-down mode entry is prohibited as long as
a Write Burst and the internal write recovery is in
progress. In case of a write command, active power-
down mode entry is allowed when WL + BL/2 +
satisfied.
In case of a write command with Auto-Precharge,
Power-down mode entry is allowed after the internal
precharge command has been executed, which is WL
+ BL/2 + WR starting from the write with Auto-
Precharge command. In this case the DDR2 SDRAM
enters the Precharge Power-down mode.
N O P
Power-Down
512-Mbit Double-Data-Rate-Two SDRAM
Active
Entry
HYB18T512[400/800/160]A[C/F]–[3.7/5]
t
XARDS
XARDS
T7
N O P
C om m and
Tn+2
tIS
V alid
Act.PD 0
(“slow exit”) depends on the programmed
(“slow exit”) depends on the programmed
T8
N O P
Power-Down
Active
Exit
Tn
N O P
tIS
tXARD or
tXARDS *)
Tn+1
N O P
Functional Description
09112003-SDM9-IQ3P
Tn+2
Rev. 1.13, 2004-05
C om m a nd
V a lid
Act.PD 1
t
WTR
is